The Nanometer CMOS Interconnect Performance Study Considering Process Variations And Scattering Effect

As the feature size of CMOS integrated circuit enters into the nano-scale phase, the interconnect performance has become a key factor restricting the design of integrated circuits. In nanometer technology, the process variations with random nature will directly result in changes in the physical structure of integrated circuits, thereby affecting the interconnect performance, which significantly affect integrated circuit functionality and performance. In addition, when the IC manufacturing technology continues to improve, it will result in decreasing interconnect size, thus produce increasingly severe scattering effect. The presence of scattering effect will greatly increase the resistivity of interconnect metal, thereby affecting the interconnect performance, such as delay and bandwidth. Therefore, to correctly analyze and design integrated circuits, we need to consider the effect of process variations and scattering effect on the interconnect performance.Due to serious influence of process variations and scattering effect, based on the equivalent Elmore delay model and the use of the polynomial chaos and the Galerkin method, this paper proposes a linear statistical RCL interconnect delay model considering process variations by using successive linear approximation method; Then, we analyzes the problem of scattering effect, and specifically discusses the effect of scattering effect on the interconnect performance. In addition, based on the prominent role of the interconnect performance on features and performance of integrated circuits in nano-technology, this paper also presents an interconnect size optimization model which optimizes interconnect performance. Hspice simulation results show that the proposed delay model and interconnect size optimization model are high precision, and the algorithms are simple. So they can be used in integrated circuit analysis and design.