Font Size: a A A

Study Of IRFPA ROIC Integrated Analog-to-digital Conversion

Posted on:2016-05-26Degree:DoctorType:Dissertation
Country:ChinaCandidate:L GaoFull Text:PDF
GTID:1108330479982362Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
With the development of infrared focal plane array technology, the larger plan, lower power and faster speed has become the main direction of development. One of the main methods used to achieve the development of infrared focal plane technology, is the realization of on-chip analog-to-digital conversion(ADC) function. The ADC is integrated into an infrared focal plane array( IRFPA) read-out circuit, thus can avoid inter chip analog signal transmission and greatly reduce the noise. At the same time, on-chip ADC can symplify the design of the system and improve the system’s speed of transmission. In the infrared focal plane read-out circuit integrated analog to digital conversion has very strong theory value and application prospect, is an important development direction of digital infrared focal plane device.This paper discussed the principle and the method of the infrared focal plane read-out circuit integrated analog-to-digital converter. Considering the performance index, the circuit structure and the realization method and principle, we select the successive approximation register(SAR) analog-to-digital converter as the on-chip analog to digital conversion of infrared focal plane readout circuit. A successive approximation register(SAR) 12 bit ADC is designed, which based on 30 um center distance. The ADC is suitable for the row(column) level of the structure of the digital IRFPA readout circuit. The design, simulation and layout of both analog and digital circuit are designed in the Cadence and Synopsys design platform. The circuit is tapout by 0.35 um 3.3V CMOS process technology in GLOBALFOUNDRIES. The actual test results of the chip in low temperature environment show that the effective number of SAR ADC is about 9bit, the switching frequency is more than 150 K Samples/s and the power is less than 300 u W. All the results meet requirements about the focal plane frame and the low power consumption of system. According to the test results, we analyzed the problems of the circuit, proposes solutions, and provide effective reference for the research work for the future. The design of SAR ADC in this paper provide technical basis for the development of digital 512 * 512 focal plane readout circuit.
Keywords/Search Tags:IRFPA ROIC, ADC, Successive approximation register(SAR)
PDF Full Text Request
Related items