Design And Test Of Irfpa-roic And Rresearch Of Dft

Infrared focal plane arrays have broad application prospects in the military, medical, industrial and scientific fields. Infrared focal plane array mainly composes by infrared detectors and readout integrated circuit. The focal plane infrared detector generates an incident voltage fluctuations after receiving infrared incident radiation at the incident position in the infrared radiation. By scanning the different pixel units of focal plane array the small voltage signals are sent to the device to read out. Readout circuit is a key technology of infrared focal plane arrays, one of the merits of its performance largely affects the infrared focal plane arrays, and the entire IR system performance. CMOS readout circuit becomes the mainstream of the readout circuit research because of its low cost, low power consumption, and many of the other advantages. Today's technology has developed into a set of infrared focal plane array infrared materials, optical, silicon micro-machining and micro-electronics technology as an integrated technology. China was involved in this area of research in the nineties of last century and is still in the pre-research phase.Our levels still have a largre gap between the Western developed countries, so developing our own technology for infrared focal plane arrays has become increasingly important.IC design technology, manufacturing technology and testing technology are known as the three key technologies in integrated circuits. Test issues should be considered as an important part in system design, and is becoming increasingly important. The better we study and understand the contents related to the design and testing, the better we design and analysis the integrated circuits, so the application of design for test is necessary.In chapter 2 I first describe the principle of the analog portion of the readout circuit, then I design the read out the sequential circuit according to the timing requirements and last have the simulation. Taking into account an array of 320X240 size is not large, I use the full-custom design approach, and propose a method using dynamic shift register, greatly reducing power consumption and area, and saving the number of MOS tube around 5000.1 have tape out it with CSMC 0.5μm DPTM single well process.In chapter 3 I make the testing plan and build a test system for the packaged chip. According to the whole circuit testing result, problems were analyzed, as a reference of the next version of the circuit design.In chapter 4 I introduce the principle of common design for test methods and propose a design for testability structures for module testing. The structure can greatly improve the module testing capacity in the analog circuit, and the smaller number of PAD leads to the chip layout area reduced. It is expected to reduce production costs.After taping out and testing and validation,it confirms that the digital circuit design is feasibility. However, the proposed design for test method remains to be further improved and verified to optimize performance and improve reliability, which is the next step of the research.