Study On Novel Power Semiconductor Devices And The Utilization Of The Edge-terminal

The development of power electronics plays a key role in the efficient usage of electrical energy and the power semiconductor devices are the core for power electronic technology. As is said that one generation of the power semiconductor device leads one generation of the power electronic technology, the development of the power electronics attributes to the innovation of the power semiconductor devices. From the early days of the birth of the power electronics to the present, various types of the power semiconductor devices have gradually come out and been developed vigorously.The power semiconductor devices are always used as switches in most cases. The ideal switch should have large blocking voltage, high conductivity, high switching speed and be easily driven. However, the performance of the state-of-the-art devices is still far away from these requirements and has a great potential to be improved. Taken silicon based VDMOS as an example, the most important problem is that Rsp rises evidently with the increase of VB, which is called as the "silicon limit". This limitation restricts the device to be used in higher breakdown voltage application field.The invention of the Super-Junction structure in 1990 s breaks the silicon limit, which enables the Rsp an order of magnitude lower than the conventional VDMOS under the same VB. Recently, another novel power device named high-k(Hk) MOSFET has been proposed. This kind of device employs high-k insulators in the voltage-sustaining region, resulting in an evident enhancement of the effective permittivity of the voltage-sustaining region and increasing the breakdown voltage. The Rsp of the Hk-MOSFET is comparable to the SJ-MOSFET.The innovation of this thesis is that new methods are proposed to further lower the specific on-resistance Rsp(s) of the power devices without affecting the breakdown and switching characteristics in comparison with the prior work. Simulation results indicate that, under the same breakdown voltage VB, the Rsp(s) of the proposed devices are about 20%~70% lower than the prior works.There are many cell patterns for the layout of the semiconductor and the Hk insulator. Obviously, the densest packed hexagonal pattern has the lowest Rsp. This paper discusses the theoretical relationship between Rsp and VB of the Hk-MOSFET with hexagonal cells, wherein the Rsp is around 20% smaller than that of using an interdigitated layout. The simulation results are coinside with the theoretical ones. For 900 V devices as an example, Rsp of the Hk-MOSFET is only 5% larger than that of the SJ-MOSFET, but has much higher robustness in charge-imbalance effect. However, the most challenging problem to manufacture Hk-MOSFET is to find an appropriate high-k material and develop the process technology.It is reported that the specific on-resistance of a vertical power MOSFET can be reduced evidently by forming accumulated carriers for conducting in the drift region. However, the accumulated charges are induced by applying a voltage to the gate in these devices, resulting in a large number of gate charges, which not only causes a higher driving dissipation, but also lowers the switching speed of device. In this paper, a new method to introduce the accumulated carriers in the drift region of a vertical super-junction device is proposed as well as the utilizing of the edge termination technology. In the proposed device, there is an integrated low-voltage power supply, which provides and stores the gate charge. Thus, the effective gate charge is decreased greatly. The simulation results of a 600 V device exhibit that the Rsp of the proposed device is only 46% of that of a conventional SJ-MOSFET with the effective gate charge being almost the same.The proposed technology discussed above also can be used for the lateral device. The characteristics of the proposed device are verified by the simulation and the results indicate that for a 600 V device, the specific on-resistance of the proposed device is only about 30% of that of a conventional Double-RESURF LDMOS with almost the same effective gate charge. Apparently, the lateral device is much easier to be manufactured in the future than the vertical one.