Simulation And Process Design Of Super Junction LDMOS Based On Charge Balance

Now, people are often accompanied by mobile phones, computers and other electronic products. In any electronic product, power supplyer is an essential component, and the power semiconductor device is a necessary element for power supplyer`s current and voltage processing. Power semiconductor devices after a development of 60 years, has formed a huge family. The new family members are constantly eroding the application market of the original nembers by their excellent electrical properties. In power semiconductor devices, the MOS device has no self thermal effect, will not happen two times breakdown, is the voltage control device, and has a simple driver circuit. These advantages make it widely used.In the design of the power MOS device, the relationship between the breakdown voltage and the onstate specific resistance is very severe. In order to solve this problem, the super junction structure is put forward. This structure not only has good electrical characteristics, but also has a good technical transfer characteristic. These advantages make it known as "a milestone in the development history of power devices". Over the past few years, the application and optimization of this structure is very popular. In the vertical sstructure, good electrical characteristics can easy get, the main job is developing the process for it.Because of the existence of the substrate assisted depletion effect, the appilication of the lateral super junction structure has been limited. From the success of the vertical structure, people have seen the huge potential of the lateral super junction structure. A variety of structures and technologies have been developed to solve this problem.Based on the previous work, this paper presents two novel device structures. The simulation software TCAD ISE 10.0 is used to design and optimize the structures. Two new types of devices are Divisiory N pillar Unbanlanced(DNU) SJ-LDMOS and N Buried Buffer(NBB) SJ-LDMOS. By simulation, the electrical characteristics of DNU SJ-LDMOS are compared with the banlanced SJ-LDMOS. Uunder the same parameters, DNU SJ-LDMOS has the onstate specific resistance decreased by 14.08%, the breakdown voltage increased by 38.74%. The parameters of the device are optimized, such as the partition density, the partition length, the number of the partitions etc. The device can be obtained that the onstate specific resistance is 46.99 m??cm2 and the breakdown voltage is 207.0V. In the same condition, NBB SJ-LDMOS, Buffer, SJ-LDMOS and the traditional SJ-LDMOS are compared. Compared with the traditional SJ-LDMOS, Buffer SJ-LDMOS and NBB SJ-LDMOS has the onstate specific resistance decreased by 27.8%, 38.1%, respectively, and the breakdown voltage increased by 11.7% and 62.6%, respectively. Compared with Buffer SJ-LDMOS, NBB SJ-LDMOS has the onstate specific resistance decreased by 21.8%, and the breakdown voltage increased by 45.5%. The parameters of the device are optimized, such as the thickness of N buried layer, the length of the N buried layer, the doping concertration of the N buried layer etc. The device can be obtained that the onstate specific resistance is 82.38 m??cm2, and the breakdown voltage is 322.8V. At last, the paper introduces the BCD process and the process flow of the traditional SJ-LDMOS, develops the process flow of DNU SJ-LDMOS and NBB SJ-LDMOS,and designs the layout of DNU SJ-LDMOS and NBB SJ-LDMOS.