Design Of CMOS Low Noise Amplifier For High Performance Microwave Radar

In recent years,the development of modern wireless communication technology has accelerated the upgrading of IOT applications.The application of intelligent equipment in the Internet of Things also greatly saves human resources and improves the quality of life of human society.It also brings new problems to people’s lives.On the one hand,the application of the Internet of Things has higher and higher requirements for the reliability and concealment of sensors.On the other hand,the collection of information by visual sensors has aroused people’s concern about privacy security.The radar sensor can extract the characteristic parameters of the object and the environment through the detection and analysis of electromagnetic waves,which can well solve the above problems.Therefore,this thesis designs a low cost,high integration and high reliability high performance microwave radar low noise amplifier by studying the Internet of Things radar and CMOS integrated circuit technology.Firstly,a novel design of Inductor Package is proposed based on Fan-out large plate-level Package(FOLP).The inductor is designed in the redistribution layer(RDL)of FOPLP,which eliminates the parasitic capacitance between the substrate and the inductor,and improves the quality factor(Q)and self-resonant frequency(SRF)of the inductor.Simulation results show that in the frequency range of 0–30 GHz,the quality factor(Q)and self-resonant frequency(SRF)of the packaged inductor designed by this method are3.34 GHz and 4 GHz higher than those of the on-chip inductor with the same size(Inductor On-Chip),respectively.Secondly,based on SMIC 0.13μm CMOS process,a 10GHz CMOS low noise amplifier is designed,and the noise figure(NF),gain and power consumption of the low noise amplifier are derived.The low noise amplifier adopts a three-stage series structure,and the input stage adopts the Cascode structure of the source degenerate inductor with the transformer as the load,so as to improve the gain,compensate the transformer loss on the chip,enhance the stability of the system,and realize the conversion from the single end to the differential signal.The second and third stages adopt the differential structure of the common-source common-gate to increase the system gain,expand the 3 d B bandwidth,suppress the common-mode noise,and improve the noise index of the low noise amplifier.In addition,the package inductance is proposed to replace the on-chip inductance as the input matching inductance to eliminate the parasitic effects of the package lead and the input PAD,improve the impedance matching flexibility,achieve better input matching,and reduce the IC area and reduce the manufacturing cost.Finally,we compares the layout design and simulation of the packaged inductor and the on-chip inductor as the input matching inductor of the low noise amplifier,respectively.The results show that compared with the on-chip inductor design,the layout area of the low noise amplifier using the package inductor design is reduced by nearly 1/4 to 650×500 um~2(Including PAD).At the same time,due to reducing the parasitic capacitance of PAD and the influence of packaging lead on the input signal,the input matching and gain flatness of low noise amplifier are better.In addition,the noise coefficient(NF)in the working frequency band of 9.4–10.6 GHz designed by the package inductor is less than 4 d B and 5 d B under typical and limit parameters,respectively.The gain is adjustable from 15 d B to 26 d B.The 1 d B compression point(IP1d B)and the third-order intermodulation distortion point(IIP3)are-10.22 d Bm and-1 d Bm,respectively.The power consumption is 10 m W～19.6 m W at 1.2 V supply voltage.