| With the development of wireless communication technologies, researches in the field of Radio Frequency Integrated Circuit (RFIC) become more and more heated. Due to the advantages like small-size, low-power-consumption and facility in being integrated with other systems, the RFIC based on Complementary Metal Oxide Semiconductor (CMOS) technology has become a pop research area in both the academic world and the industry. And it is known that7.1-7.9GHz is widely used in point-to-point communication system. Therefore, the purpose of this thesis is aiming to design a C-band CMOS low noise amplifier (LNA).Low noise amplifier is a key component in the front-end of RF transceiver, its noise, gain and linearity performance will directly take a significant impact on the whole system. That is also the key point of LNA design.Firstly, this thesis introduces the subject of background, significance of the research and the research situation at home and board of low noise amplifier.Secondly, on the basis of relative references, this thesis gives analysis to classical noise theory of two-port network, MOSFET noise parameters and performance parameters of low noise amplifier. Then compared to common-used structures. LNA with inductive source degeneration is employed to determine the optimum device width in fixed power consumption.Thirdly, the commercial software Advanced Design System (ADS) is used to simulate single stage LNA, such as common-source topology, common-gate topology and cascaded-stage topology. Compared with three topologies, Only cascode low noise amplifier can get both the power-matching and the noise-matching conditions. Then to get better gain, two-stage LNA is further designed in this thesis.Finally, to reduce power dissipation, direct current (DC) split and current-reuse technology is used in conventional cascode LNA and two-stage LNA. respectively. It is shown that improved topology can decrease the whole power consumption with equivalent performance of the old one. |
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