Design Of A Rail-to-rail Current Steering DAC

In the field of audio and video signal processing,radar imaging,and automotive electronic controlsystems,Digital to Analog Converter（DAC）has been widely used as an interface to connect digital and analog signals.With the development of integrated circuit technology and communication technology,the demand for high-performance and high-speed analog-to-digital converters is increasing.The thesis first elaborates on the circuit structures and working principles of different types of DACs,introduces the main performance indicators of DACs,and compares the advantages and disadvantages of DACs with different structures.A 10 bit 500 MHz rail-to-ail current steering DAC is designed for the application requirements of rail-to-rail output.Through a dual current source array and four output channels,the output voltage range of PMOS current source and switch array is from ground to₂¹(1,and the output voltage range of NMOS current source and switch array is from₂¹(1to(1.The Automatic control detection unit（ACDU）module designed in this thesis automatically selects the optimal output control turn after the input code is judged,so that the circuit can achieve high-performance rail-to-rail voltage output.The designed DAC adopts a"5+4"segmented decoding method and a symmetric decoder structure,and uses the highest bit of the code as the judgment bit to determine whether the remaining other bits are normal decoding or reverse decoding.In addition,the next highest five and lower four bits use thermometers and binary decoding,respectively,which reduces circuit complexity and improves performance.The switch array adopts symmetrical dummy transistors to reduce clock feedthrough and improve circuit operation speed through non overlapping clocks.The reference voltage adopts a low-voltage bandgap reference structure,and the voltage to current conversion uses a low-voltage cascode structure,which enables the reference module to generate a high-precision current source.The circuit and layout are designed in 28 nm CMOS technology.The analog circuit is powered by a 1.8 V power supply voltage,while the digital part is powered by a 0.9 V power supply voltage.The post-simulation results show that the static characteristics of the designed DAC are DNL=±0.6 LSB,INL=-0.4-1 LSB.At an input frequency of 100.0977 MHz and a clock frequency of 500 MHz,the SFDR of the final output signal is 66.4 d B,THD is-59.8 d B,SNR is 64.38 d B,ENOB is 9.4 bit,and the total power consumption of the circuit is 71.3 mW.