Modification Of Compact Modelling Of Carbon Nanotube FETs And Its Circuit Simulation In SPICE

The development of the microelectronics industry has entered the post-Moore era.Silicon-based MOSFETs are limited by short-channel effects,and their proportional size may stop shrinking within 5 years.Carbon nanotubes(CNTs)have excellent performance,and CNTFETs have attracted wide attention due to their low power consumption and high integration,and are regarded as the most potential replacements for Si-channel MOSFETs.To facilitate the design of CNTFET circuits,compact models of CNTFETs that are compatible with existing EDA platforms such as SPICE are required.The thesis proposes a compact model of top-gate CNTFET,which is based on the existing Stanford top gate CNTFET model.The nine-capacitance network model of the intrinsic channel region in Stanford model is simplified to a four-capacitance network.In this thesis,different doping level in the source/drain region is considered,and the outer fringe capacitance between the intrinsic channel and the doped source/drain region is established.Finally,a compact model of wrapped gate CNTFET is established for the first time.We simulated top gate and wrapped gate CNTFETs with channel length of 15 nm using HSPICE,studied the influences of structural parameters such as the diameter,number of CNTs and their gap on I-V characteristic,transconductance and cut-off frequency.The results are compared with reported experimental data and physical simulation data.The simulation results show that under the same physical size,top gate CNTFET has a larger cut-off frequency while the saturation current of the wrapped gate CNTFET is larger.We also simulated the CNTFET-based inverter and other two-input basic logic gate circuits in HSPICE.Compared with the circuit simulation based on Stanford model,we added the influence of the gate-to-electrode coupling capacitance,which makes our modeling more realistic and more suitable for the design and development of CNTFET circuits.The influences of the FET structure parameters on the circuit delay and power consumption are analyzed.The basic logic gate circuit based on wrapped gate CNTFET has smaller delay and is more suitable for high-speed circuit design.The basic logic gate circuit of top-gate CNTFET has smaller power consumption and is more suitable for low-power design.Finally,we try to design a basic logic gate circuit on a set of CNT parallel arrays,consider the impact of metal carbon nanotube interconnects and device layout,predict the circuit characteristics,and lay the foundation for practical realization in the future.