Modeling And Optimizing Of Carbon Nanotube Based CMOS Logic Circuit

Table look-up model is a method usually used in modeling silicon based CMOS (Complementary Metal-Oxide-Semiconductor) logic circuits. Because it directly makes use of electrical characteristics of single device from experiment to establish the model, we do not have to consider complex current-voltage function. This method is useful for us to establish the CNTFET (Carbon Nanotube Field Effect Transistor) model.We modified the calculating method of the gate capacitor, so the semi-empirical table-lookup model can model the top-gate Carbon nanotube based CMOS field effect transistor logic circuits. After we input the experiment data (some data had been smoothed) and parameter from calculation, we successfully simulated CNT CMOS inverter, NAND, NOR and adder based on the semi-empirical table-lookup model. Simulation results were verified by the experimental results and good agreement was achieved. Successfully modeling the adder proved the CNTFET in our experiment can meet the need of designing the complex VLSI logic circuits. Compare to other simulating methods, we proved this method is more proper for simulating the CNT CMOS logic circuits.Based on table-lookup model, CNT CMOS inverters were researched through DC analysis and TRAN analysis in SPICE. The effects of supplied voltage and the threshold voltage to the power and the delay characteristics of the inverters were investigated, and optimum strategy was given. In addition, the effects of supplied voltage to delay characteristics of the inverters were investigated and optimum strategies for NOR and NAND logic circuits were given by the simulation using the semi-empirical table-lookup model.