Research Of AVS3 Video Decoding Image Reconstruction Technology

Video coding technology reduces the amount of data required for video code streams by compressing the original video data,while ensuring that video quality is not compromised.For the needs of applications such as ultra-high-definition broadcasting and film,panoramic video,augmented reality/virtual reality,autonomous driving and smart cities,the China Digital Audio and Video Codec Standard Working Group(AVS)has developed the third-generation video coding standard AVS3 to improve the compression rate and maintain video quality to support applications such as ultra-high resolution(above 4K),panoramic video and 3D video.Based on the analysis and summary of video coding and decoding architecture,existing coding and decoding optimization techniques and typical algorithms,the paper designs,verifies and optimizes the most important mid-inverse transform and intra-frame decoding techniques in the image reconstruction segment of AVS3 video decoding.The main work in the full paper is as follows:(1)The decoded image reconstruction code in the AVS3 reference software HPM4.0 is analysed and an in-frame prediction and inverse transform separation structure with software simulation of hardware data transfer is proposed.The analysis of simulation results proves the correctness of the proposed algorithm structure,determines the hardware design interface structure,and provides test data for simulation verification.(2)Based on the research and analysis of the inverse transform algorithm and the overall architecture,the design ideas of the 1D inverse transform module,the transpose module and the pixel position rearrangement module are presented respectively.For the inverse conversion module,a hardware optimisation design using butterfly transform and additive tree multiplier is presented;for the transposition module,a fast transposition scheme based on single-port SRAM is proposed;for the pixel position rearrangement module,an optimisation design using SRAM array structure is presented.Finally,simulation verification,hardware resource analysis and processing speed tests are carried out for the 2D inverse conversion module,and it is determined that the proposed design scheme does not use DSP resources,consumes 35354 ALMS,can be adapted to a wide range of 4-6size inverse conversion operations,and the processing speed meets the demand for 8K60 fps real-time decoding.(3)Based on the research and analysis of in-frame decoding,a prediction data structure based on 4×4 sub-blocks of 16 pixels in parallel is first proposed.The hardware optimisation design of the reference pixel cache and angle prediction is then carried out,a suitable reference pixel cache size is proposed,and the angle prediction process for a specific angle is optimised according to the characteristics of angle prediction,and an optimisation scheme for multi angle parallel prediction is proposed.High Level Synthesis(HLS)techniques are also applied to optimise the speed and resources of the overall in-frame decoding module.Finally,the simulation verification,hardware resource analysis and processing speed test of the intra-frame decoding module confirm that the proposed design reduces the number of operation cycles by 16% on average compared with that before optimisation using HLS technique,supports 33 prediction modes using 68628 LUTS,23194 FF,and the processing speed meets the demand of 8K60 fps real-time decoding.