Research And Design Of AVS-based Video Decoding Module

With the development of digital signal processing technology and computer technology, the tide of digital video sweeps all over the world. The application and entertainment needs for high-definition video are daily on the increase. In order to solve a series of problems including video quality, storage space and real-time, people pay more efforts to research high-efficient video compression standard and hardware video decoder. As a source standard with China’s independent intellectual property rights, AVS has advanced, autonomous, open characteristics, and a broad marketing prospect. Consequently the study of AVS decoding hardware implement has great significance.In this paper, researching the algorithm characteristics set forth in AVS, the parallel pipeline of video decoder has been planned, and the decoder structure which is more suitable for hardware implement has been designed. Specific content includes:(1) Variable length decoder. After researching the variable length decoding part of AVS standard, barrel shifter is designed and implemented to output data with corresponding length, and a series of lookup tables are used to decode variable length code.(2) Residual coefficient processing. A buffer FIFO is inserted to implement two-level pipelines after inverse quantization. Inverse scan, IDCT and transposition run in a 8 X 8 register matrix, and eight sets data of both row and column transformation can be processed in the same time. This method takes no memory source and cuts down the clock periods used by reading and writing the memories.(3) Intra prediction and Reconstruction. After analyzing the algorithm of AVS intra decoding, extracting the general characters of different modes’ algorithm and arranging on-chip memory space appropriately, a basic arithmetic unit is devised to fulfill predicted pixel’s calculation of most prediction modes, when calculating the predicated value of pixels. A Plane-mode arithmetic matrix is designed to complete the calculation for the more complicated Plane-mode.(4) Loop filter. This paper proposed a new filtering order and a rational source arrangement of on-chip dual-port RAM, after analyzing the algorithm of loop filter. The pixel filter and pixel transfer works in parallel. This method accelerates the loop filter speed and cuts down the clock periods.(5) Inter prediction motion vector. Command words and flags are used to classify the numerous inter prediction modes and divide methods. The subsequent MV calculating module jumps into different branches and invokes calculating units. During MV calculating, a shared calculating unit is designed to implement some frequent used complex formulas by Time-division multiplexing mode.This paper uses Verilog to design each module, and verifies several key hardware modules by comparing with rm software, ModelSim simulation, FPGA verification. The analysis shows that the design of modules can meet the requirement of standard definition AVS video.