Research On High Speed And High Precision Readout Technology Of Large Array Cmos Image Sensor

CMOS image sensor(CIS)is increasingly favored because of its low power consumption,high integration,low cost and many other advantages,and gradually replaced the charge coupled device CCD,Based on the demand for high-resolution CMOS image sensors in satellite systems,industrial automation,surveillance systems and other military industries,large array CIS has broad market prospects and research value.However,due to the rapid increase of pixel array,many problems need to be solved.For example,when the resolution of CIS reaches hundreds of millions of pixels,the overall size of the super-large array CIS is significantly larger than the typical mask size(26mm×33mm).At this time,how to balance the splicing process and carry out the consistent design of the left and right row drive,how to overcome the parasitic effect of the ultra-long column bus in the pixel on the readout speed?The high dynamic design with small pixel size is also taken into account while maintaining bilateral drive consistency and high-speed readout.In this dissertation,we focus on the above bottleneck problems to provide theoretical guidance for high-speed and high-precision readout of CIS front-end.The main contributions of this paper include:Based on the 8T pixel,the principle of the improved dynamic range of the potential well capacity adjustment technology of the PIN-Photodiode(PPD)is explored,and the physical equivalent model is used to simulate the method in this paper.Experimental results show that compared with the dynamic range of traditional pixels,the proposed technique can improve the traditional dynamic range by more than 3.6 times.It lays the foundation for the realization of large array CIS with high dynamic range.This paper proposed a method of bilateral coherence driving for mosaic-based CMOS image sensors.When designing row control for pixel arrays of high-resolution CMOS image sensors,the structure of bilateral signal line drivers must be considered.However,as the size of the pixel array increases,the stitching technology must be used,which leads to the high cost of the traditional clock tree synchronization technology.In addition,the inconsistency of the bilateral driver circuit will cause the current pass-through phenomenon and the inconsistency of the column bus.In order to solve the above problems,this paper proposes an adaptive delay detection and accurate compensation method,which realizes the consistent driving of both sides of the pixel array on a 150M pixel,77mm×84mm CIS.Considering the actual parasitic parameters,the post-simulation results show that the inconsistency of bilateral row drive is reduced from more than 17.5ns to less than 2ns(one clock cycle)at 500MHz clock frequency,and the consistency is improved by more than 8.7 times.It provides a guarantee for the frame rate of the mega-array image sensor with the scale of 100 million pixels to reach more than 10 frames.An adaptive acceleration method for column bus establishment is proposed.This paper explores the problem of the large parasitic resistance and capacitance on the column bus of the pixel array in the large area CMOS image sensor,which leads to the change of the dominant factor of the column bus signal establishment speed and seriously affects the readout speed.In order to solve this problem,this paper proposes an adaptive tail current acceleration discharge circuit,which accelerates the signal establishment process of the column bus through real-time tracking of the analog signal establishment process without introducing additional buses,and improves the readout speed of the ultra-long column bus by more than two times.The experimental results show that,compared with the traditional CIS design method,the rise setup time is shortened from 3.2μs to 1.5μs,and the fall setup time is shortened from 10.2μs to 5.1μs under the condition of 28pF parasitic capacitance and 20kQ parasitic resistance generated by 100 million pixels using the proposed method.On the one hand,the frame rate of CMOS image sensor is increased to 10 frames,on the other hand,the sampling interval time of correlation double sampling is compressed,so that the frequency range of noise suppression is widened.In summary,the research work carried out in this thesis focuses on the problems encountered in the design process of CIS of super large pixel array.Without changing the traditional pixel structure,the PPD potential well capacity adjustment technique explored in this paper can improve the dynamic range by more than 3.6 times with a low implementation cost while ensuring a piecewise linear response.In this paper,an adaptive delay detection and accurate compensation technique is proposed to solve the problem of bilateral row drive inconsistency caused by the application of the Mosaic technology with low power consumption and area.The corrected inconsistency is less than 2ns.The adaptive tail current discharge circuit proposed in this paper solves the problem of slow signal establishment caused by the parasitic effect of column bus to some extent,and improves the readout speed of large array CIS with the additional power consumption of less than 10μW on the premise of barely affecting the pixel output accuracy.So that the CIS frame rate of 12288×12288 resolution can reach 10FPS.