Research On High Dynamic Range Readout Integrated Circuit For High Sensitivity Infrared Focal Plane Array

High sensitivity with m K-level temperature detection capability is an important direction for the development of the infrared focal plane array(IRFPA).To achieve this goal,the readout integrated circuit(ROIC)of the infrared focal plane must have large charge capacity and high dynamic range.With the continuous expansion of the focal plane array and the shrinking of the pixel area,and the limited capacitance per unit area and output voltage amplitude of the CMOS process etc.,the design of ROIC with large charge capacity and high dynamic range faces the difficulties and challenges.This article makes a detailed analysis of the charge capacity and dynamic range parameters of the ROIC that required to achieve the cooling infrared focal plane with m K-level temperature detection.Through literature research and comparison,the charge packet count ADC structure,linear-logarithmic structure,and traditional structure are analyzed.These are the three ways to realize the goals of large charge capacity and high dynamic range in the ROIC.The charge packet count ADC ROIC is based on the current-pulse modulation method.Each pulse is a charge packet.When the integration time is set,the number of charge packets can be obtained through a counter to obtain an effective signal.Based on the CSMC 0.18?m 1P6M process,a charge packet count ADC ROIC with the pixel size of 512×32 and the center distance of 30?m×30?m are designed.The maximum charge capacity is 2.4 Ge~-?8.9 Ge~-and adjustable.The design of the unit cell circuit is necessary to balance performances and transistor resources in the limited area.Through a comparative design,the unit circuit uses a DI injection stage structure and a two-stage open-loop op amp comparator with a lower delay and adjustable operating current.The simulation results of the comparator show that the delay can reach 14 ns.The digital part uses the high-speed,low-power-consumption TSPC D-flip-flop to form a 16-bit counter.The unit cell circuit realized the integration of 417 MOS transistors in an area of 30?m×30?m.The output interface of the ROIC uses a standard LVDS output interface,which can achieve high-speed output of all data.The test results of the TEST structure show that the designed LVDS interface has an output speed of up to100 MHz and the linearity of the output signal is greater than 99.9%.The charge packet count ADC ROIC has been coupled with a long wave Hg Cd Te IR detector.The focal plane array test results show that the peak output noise is 4 and the NEDT reaches 8 m K at the conditions of F#2 and integration time 41.01 ms,when the working temperature is70 K.The dynamic range reaches 84 d B.In the linear-logarithmic ROIC,the logarithmic response mode is realized based on the logarithmic relationship between the gate-source voltage and the drain-source current of the MOSFET in the sub-threshold region.The logarithmic response mode can greatly improve the dynamic range of the circuit.But because the logarithmic mode responds poorly to weak signals and the signal-to-noise ratio is low under weak signals,it is necessary to combine the linear response mode to obtain weak signals with high signal-to-noise ratio information.The linear-logarithmic ROIC in this article uses the Global Founfry 0.18?m 1P6M process.The ROIC with a size of 16 pixels and a center distance of 30?m is designed for verification.The injection stage structure uses a BDI structure and combines two MOS transistors for logarithmic response.The readout circuit can automatically switch between linear response mode and logarithmic response mode.The test results show that the noise of the circuit in the linear response mode is 0.45 m V and the sensitivity of the circuit in the logarithmic response mode is86 m V/dec.The dynamic range of the circuit reaches 137 d B,and the dynamic range of the readout circuit with a coupled Hg Cd Te IR detector is greater than 102 d B.The ROIC of geostationary interferometric infrared sounder(GIIRS)is used for FY-4 to obtain more abundant information of the three-dimensional direction of the atmosphere.This article uses the CSMC 0.5?m DPDM process to design a 128(16×8)channel ROIC.The ROIC increases the charge capacity and dynamic range by increasing the integration capacitance and reducing the circuit noise.Since the geostationary interferometric infrared sounder needs to work in the geosynchronous orbit,the working environment has a large temperature difference between day and night,the background environment signal also changes greatly.Therefore,the injection structure of the circuit uses a high-performance CTIA structure and correlated double sampling has been used to reduce noise.In addition,the integration capacitor of the circuit is adjustable into four different capacitance.The maximum integration capacitance is 16 p F,so the maximum charge capacity of the circuit can reach 130 Me~-.The test results show that the output swing of the ROIC is 2.6 V,the noise is 0.14 m V,and the dynamic range reaches 85.4 d B.The noise of the focal plane is 0.43 m V,and the dynamic range reaches 75.6 dB.