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Design Of Wide Dynamic Range Readout Circuit For High Speed Linear CMOS Image Sensors

Posted on:2017-09-15Degree:MasterType:Thesis
Country:ChinaCandidate:C J YangFull Text:PDF
GTID:2348330515963882Subject:Integrated circuit engineering
Abstract/Summary:PDF Full Text Request
Linear array image sensors obtain continuous images by scanning the target objects in one direction or in a loop,thus,they are usually used in industry detection,aerial photography,and satellite imaging.More and more applications require high speed scans to improve detection efficiency,and in some cases,the target objects are moving fast.Both conditions increase the demands of high line rate linear image sensors.Moreover,the target scene may contain high light and low light objects,and the dynamic range of the targets usually exceeds 90 dB.However,the dynamic range of traditional readout circuits is limited to 60–70 dB.A wide dynamic range readout circuit is expected to cover at least a detecting range over 90 d B to capture all the possible information.Therefore,the readout circuits of linear array image sensors require a wide detecting range and high speed readout.This thesis presents a dynamic range enhanced readout technique with a two-step time-to-digital converter for high speed linear CMOS image sensors.A multi-capacitor and self-regulated capacitive trans-impedance amplifier structure is employed to extend the dynamic range.The gain of the CTIA is auto adjusted by switching different capacitors to the integration node asynchronously according to the output voltage.A column-parallel ADC based on a two-step TDC is utilized to improve the conversion rate.The voltage-domain is converted to time-domain by ATC,then the time signal is converted to digital code by TDC which is divided into coarse phase and fine phase.An error calibration scheme is also proposed to correct quantization errors caused by propagation delay skew within-Tclk~+Tclk.A linear CMOS image sensor pixel array is designed in the 0.13 ?m CMOS process to verify this DR-enhanced high speed readout technique.The post simulation results indicate that the dynamic range of readout circuit is 99.02 dB and the ADC achieves 60.22 dB SNDR and 9.71 bit ENOB at a conversion rate of 2 MS/s after calibration,with 14.04 dB and 2.4 bit improvement,compared with SNDR and ENOB of that without calibration.
Keywords/Search Tags:CIS, wide dynamic range, two-step TDC, error calibration
PDF Full Text Request
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