As the core component of imaging system,image sensor is widely used in industry,military,medical and other fields.Its performance also restricts the improvement of the performance of the whole imaging system.With the continuous development of technology in various fields,people’s demand for high resolution and high-speed CMOS image sensor is growing.When the resolution of image sensor is increasing,the size of pixel array is increasing.The parasitic effect increases significantly,and so does the ramp non-uniformity error.In this paper,the influence mechanism of parasitic effect on ramp non-uniformity is analyzed theoretically and modeled mathematically.Correction methods for ramp uniformity are proposed.On the one hand,aiming at the special architecture of CMOS image sensor with large array,this paper systematically analyzes the influence of parasitic parameters on the non-uniformity of global ramp signal under the global ramp architecture,and establishes the corresponding circuit model.A global ramp uniformity correction method based on on-chip adaptive error storage and real-time compensation is proposed.The proposed method adaptively stores the ramp nonuniformity errors in the column level readout circuit and corrects the ramp signal in real time according to the stored ramp non-uniformity errors.On the other hand,the influence mechanism of parasitic parameters on the non-uniformity of circuits generated by multiple ramps is analyzed and the error simulation model is established.On this basis,a multi-ramp uniformity correction method based on dynamic adaptive modification on chip is proposed.The proposed method ensures that the adjustment accuracy of unit capacitance is 1LSB,and realizes accurate correction by unit capacitance according to the error detection results.In this paper,based on 55 nm-1P4M CMOS technology,the chip circuit and layout design of an 8192×8192 large array image sensor are completed.Considering the actual parasitic parameters,the uniformity correction method of ramp circuit studied in this paper is verified in the system.The frame rate is 50fps,the pixel size is 10 μm×10 μm,the voltage range of ramp signal is 1.4 V,and the resolution of ramp signal is 12 bit.The full-chip CFPN is reduced from 2.21%to 0.006%.It provides a theoretical basis for the design of high speed and high precision CMOS image sensor. |