Uncooled Infrared Focal Plane Array Of Fpga-based Non-uniformity Correction

Uncooled Focal Plane Array (UFPA) is corrently one of the most active focuses in the infrared thermal imaging technology. It not only has been given fully attention in military, but also has been widespread concerned in civilian areas. The response of each cell in UFPA is different because of the limit of the detector's materials and the manufacturing technology. Also there may be some disabled cells in the UFPA. These lead to the non-uniformity of the infrared image and impact the detection performance of infrared imaging system. Therefore, the non-uniformity correction has been a crucial issue in the infrared thermal imaging technology. Correcting the non-uniformity via extra circuit can effectively enhance the detecting capability.There is a large amount of non-uniformity correcting algorithms proposed in papers at home and abroad. In this paper, the representative algorithms are introduced and their characteristics are analysed. On the basis of the analysis the calibration-based non-unifomity correction algorithms are selected to be used in real-time non-uniformity correcting system. Whereas, in the calibration-based correcting algorithms,one-point and two-point correction can not get enough precision,so multi-point correction is needed. In multi-point correction, the judgement of radiation range which is the keystone needs much data to compare with. When implementing multi-point correcting algorithm by circuit , these data need to be stored in memory. Thereby, the non-uniformity correcting system becomes more complex and the cost of system is increased. In this paper a new judgement of radiation range is presented on the analysis of the monotone increase of UFPA cell response. It is proved that the new method can get nearly the same result as original multi-point correction, and it cost less because much data is not necessary to memorize.A real-time non-uniformity correcting system based on FPGA which implements the new method is carried out in Verilog HDL. Also the circuit diagram is synthesized out by compilation of the Verilog HDL codes using Synplify. The system's timing and functional simulation is accomplished by using ModelSim. The result shows that the non-uniformity can be corrected.