Research And The Design Of 120MS/s Low Power Successive Approximation Resister ADC

With the rapid development of technology in the fields of wireless sensor networks,portable detection instruments,and implantable biomedical devices,users of sensor nodes and medical device terminals have increasingly high requirements for cruise time and high transmission efficiency.The successive approximation A/D converter(SAR ADC),due to its advantages of simple structure,smaller area,and lower power consumption,is developing rapidly in the context of the increasing demand for high-speed and low-power applications in the market.This article conducts extensive research on high-speed and low-power ADC,and summarizes the design methods of its circuits and systems.On this basis,a12bits-120MS/s high-speed low-power fully differential SAR ADC was designed.In terms of speed improvement,the control logic adopts asynchronous logic structure for acceleration;Insert redundancy into CDAC to reduce the charging time requirements of high-order capacitors,and adopt a customized layout design of capacitors to minimize charging and discharging time as much as possible;The comparator uses a fully dynamic high-speed structure to achieve a working speed of 3GHz while ensuring accuracy.In terms of reducing power consumption,the overall use of 1.1V low voltage power supply;A high linearity gate voltage bootstrap switch operating under low voltage conditions has been designed;The CDAC switch is controlled using a highly energy-efficient Vcm based switching strategy based on capacitor splitting technology for improvement.To meet the practical application needs,a second-order compensated bandgap reference has been designed for this circuit.This article establishes a behavioral level model for a 12 bits SAR ADC,and uses this model for power consumption and linearity analysis;Provide guidance for system design.The structure designed in this article is implemented using SMIC40 nm technology,with a power supply voltage of 1.1V.Performance simulation was conducted at different Process corners,and the results showed that ENOB: 11.42 bits SFDR: 81 d B,Fo M value: 7.45 f J/conv.step at 120 MHz sampling rate.Finally,the overall layout design of SAR ADC was completed using the SMIC 40 nm process and post simulation was conducted.