Research And Design Of A High Power Supply Rejection Ratio LDO With A Digital Auxiliary Module

Low dropout linear regulator(LDO)is widely used in portable,medical and automotive applications,as an extremely low-cost power management module.With the development of System on Chip(SOC),the size of device is becoming smaller and smaller and the power supply voltage is becoming lower.The ripple in the power supply cannot be ignored in noise sensitive modules,such as high-precision Analog-Digital Converter(ADC)and Phase-Locked Loop(PLL),which pose strict requirements for the power supply rejection ability of the LDO.On the other hand,the performance of analog circuits deteriorates with the reduction of device size,while the performance of digital circuits improves proportionally with the reduction of process size.Therefore,the digitization of analog circuits has become increasingly popular in recent years,and there are more and more researches on digital LDO.Based on the above background,this thesis designs a high power supply rejection ratio(PSRR)analog LDO with a digital auxiliary module.The main work is as follows:(1)A theoretical analysis was conducted on the PSRR of LDO.Based on the analysis results,it was found that making the small signal ratio of the gate voltage of the power transistor to the input voltage of the LDO close to 1 can effectively improve the PSRR.A traditional method is to use a diode connected MOS transistor in series with a common source amplifier structure.However,this method becomes less effective as the load current increases.An improved structure is proposed to address this issue,which is using a diode connected MOS transistor in series with a cascade structure.This method only adds one common source and common gate transistor,solving the problems in traditional solutions.The PSRR before and after improvement are 65 d B and 76 d B,respectively,resulting in an improvement of 11 d B.(2)The stability problem of an analog LDO is analyzed.The phase margin of the analog LDO is low under light load condition.The traditional solution of this problem is to add a large load capacitor,but this solution decreases bandwidth and is not conducive to chip integration.This paper proposes a digital auxiliary module that helps the analog LDO to achieve good loop stability over the full load range by changing the tail current of the error amplifier under different load conditions.The phase margin under no-load(the load current is 0)condition is increased from 43° to 77°,resulting in an improvement of 34°;(3)Using the above two innovative methods,a high PSRR analog LDO with a digital auxiliary module is designed.Use cadence software,build the circuit based on smic0.18μm technology and do the simulation.The proposed LDO operates in a temperature range of-40 ℃ to 125 ℃,has a minimum temperature coefficient of 6.929 ppm/℃and a minimum quiescent current of 37.91 μA.Without load capacitance,the LDO achieves a phase margin larger than 70° within the full load range.What’s more,the minimum load regulation is 0.1293 m V/m A and the minimum line regulation is 0.6162 m V/V.The DC PSRR is 77 d B,the whole circuit achieves a FOM of 24.975 fs.