Hardware Design And Verification Of Intra Prediction Technology In H.266

Versatile Video Coding(H.266/VVC)is the last multi-functional video coding standard developed jointly by the Video Coding Experts Group and the Moving Image Experts Group in the Video Coding Standardization Organization.Compared to the previous HEVC standard,H.266/VVC can improve video compression by nearly 50%,but the complexity of coding and decoding is greatly increased.This article first studies VVC intra prediction,and then analyzes the algorithm and performs hardware circuit structure design with the expanded angle prediction mode,new block partitioning method,and new technology in VVC.Finally,verifying and synthesizing the designed module.Firstly,designing hardware architecture circuit for VVC intra prediction module.With the technology of the newly added or expanded Chroma Separate Tree,block partitioning method,Intra Sub-Partitions,Multiple Reference Line,and more angular prediction modes in intra prediction,Analyzing Angular Predicton,Position dependent intra prediction combination,Cross Component Linear Model,and Matrix Weighted Intra Prediction for hardware structure design by Verilog HDL.First,Position dependent intra prediction combination and Angular prediction are designed by using module reuse,special processing elements,two-stage mode,look-up table,and pipeline,and Position Dependent Intra Prediction Combination module is the submodule in Angular module.Then,Matrix Weighted Intra Prediction is designed by using module reuse,special processing elements,two-stage mode,and look-up table.The look-up table module is a submodule of the Matrix Weighted Intra Prediction module.Finally,Cross Component Linear Model is designed by using module reuse,special processing elements,state transfer,two-stage mode,and pipeline.And the designed are instantiated as submodules of the intra prediction calculation module.The hardware structure design of the above algorithms is completed.Then,performing simulation and synthesis of prediction value calculation module.Based on the characteristics of intra prediction calculation module,hardware simulation environment is build with Verilog HDL.The designed module is verified and synthesize by using Synopsys’simulation software VCS and Synopsys’synthesis software DC.After using VCS to perform functional simulation verification of the designed module,the next work is analyzing simulation waveform and comparing the simulation printed data and generated images with the printed data and generated images of the H.266/VVC reference software.So that the simulation results can be confirmed and the performance of decoder is 8K30FPS in 800MHz clock domain.The synthesis of the intra prediction calculation module is performed by using TSMC-12nm device library and 800MHz clock constraint.The synthesis result shows that the intra prediction calculation module has 224,908 cells and its area is approximately 83343μm~2,which confirming that the result is in line with design expectations.