Design And Implementation Of Intra Prediction And Loop Filter In AVS Video Decoder

Audio Video coding Standard(AVS), independently developed and owned by China, is a fundamental standard in digital TV, IPTV and other audio/videl based systems. AVS Part2, the video part, defines the highly efficient second generation video coding technology. It has coding performance close to H.264. Moreover, its implementation is simple and easy. Although the coding efficiency of the AVS is better than previous standards, for some real-time applications, the complicated computational characteristics lead great challenges for today's VLSI implementation.Based on analysis of Advanced Coding of Audio and Video Standard, especially intra-prediction and deblocking filter, this paper introduces the design of Intra prediction and deblocking filter. The 8×8-block level pipeline is adopted to improve the real-time throughput. Sliding window is designed to fetch reference pixels. Eight parallel processing elements are employed to handle eight pixels. Plane mode carries out prediction based on scheme of systolic array. A five-stage pipeline is adopted to improve throughput. A hierarchical memory organization is proposed to organize pixels, which includes on-chip memory and AHB-based SDRAM controller. The hybrid edge filter order is developed to deal with pipeline hazards. Transposition module is suitable to transposing pixels. The pipeline with gated clock is to reduce power.The Top-down design method is used in whole design. The design is described in Verilog and a software reference model is made based on RM52j. According to Advanced Verification Methodology, testbench is constructed to functionally verify the design by using SystemVerilog, which uses transaction-level strategy, constraint-random and coverage driven methodology. The testbench improves the verification efficiency and reusability.Function simulation has been completed on each module by using VCS and ModelSim. Based on appropriate strategy of synthesis and method of optimization, two modules are synthesize by using SMIC 0.18μm CMOS technology library.The verification and simulation results indicate that the design of Intra-prediction and Deblocking-filter has achieved requirement.