Reliability Characterization And Modeling Of 0.18μm BCD Process Power LDMOS

With the continuous development of semiconductor technology,the integration of chip is increasing.However,the improvement of integration also brings many difficulties.More and more devices can not meet the requirements of high performance and high reliability of circuit.This is because the feature size of the device decreases with the progress of manufacturing technology,but the reduction of the feature size does not result in an equal proportion reduction of the working voltage.This also means that the smaller the size,the greater the pressure on the device,and the greater the probability of reliability problems on the device.Power devices have the characteristics of high voltage and high current,which causes the potential reliability problems.In order to clarify the impact of reliability problems in the application of devices,a reliability model for 0.18 um BCD power LDMOS is presented,which can accurately characterize the self-heating effect,hot carrier injection effect(HCI),and negative bias instability(BTI)on devices.At the same time,the parameters of the reliability model are extracted based on the reliability test data of the device.Finally,the integration of the reliability model and the simulation validation are implemented based on VerilogA language.The main work and research results of this paper are as follows:1.For power LDMOS with 0.18 um BCD process,DC characteristics at different temperatures have been tested,analyzed and characterized,and a compact physical model of SPICE for LDMOS has been established and parameters have been extracted.The model error is less than 2.46%.On this basis,an analytical physical model for the self-heating effect of power LDMOS is established,which can accurately characterize the output characteristic curve reduction caused by self-heating effect at high bias voltage,and reduce the model error from 2.46% to 1%.2.The physical mechanism of power LDMOS degradation caused by HCI and BTI effects is explored.Based on the theory and simulation analysis,the corresponding degradation model is established and the device life prediction is achieved.First,based on the constant stress accelerated life test,the reliability degradation tests of N-LDMOS and P-LDMOS are completed.On the basis of investigating the threshold voltage change caused by the HCI and BTI effects on the two types of devices,the corresponding reliability model is established.Based on the measured data,the work of model parameter extraction,model validation and device life prediction are completed,and the model error is less than 5%.3.Based on Verilog-A language,the self-thermal effect model,HCI effect model and BTI effect model of power LDMOS are embedded into the DC SPICE model of devices,and the simulation is completed in the HSPICE emulator.The error of selfheating model is less than 1.27%,and that of HCI and BTI models is less than 1%.Finally,the circuit is simulated using the reliability model,and the simulation results are in accordance with the expectations.This paper provides a simple and effective way to characterize the reliability of power LDMOS,which has important reference value for the establishment and application of the reliability model of power LDMOS.