Research Of Ultra Deep Submicron SoC Embedded Reliability Failure Prediction Technology

Due to the rapid development of semiconductor process, the integrated circuittechnology has stepped into Ultra Deep Sub-Micron regime, which makes integratedcircuits (IC) more functionality and compact. ICs are developing towards higherperformance and higher reliability from its birth. With the scaling device dimensionaland the boosting performance, the traditional reliability failure modes such as,Time-Dependent Dielectric Breakdown (TDDB), Hot Carrier Injection(HCI),Electro-Migration(EM), their influence on MOS devices and circuits reliability don’tmitigate, unfortunately, previously negligible failure mode, Negative Bias TemperatureInstability （NBTI）, has been more and more dominative. Therefore, in somehigh-reliability-demand fields, reliability failure threatens the security of SoCs (Systemon Chip) or systems, even if the failure of a circuit can induce great loss or catastrophicsequent. A new SoC reliability test and lifetime prediction technology is presented inthis dissertation. Aimed at reliability failure mechanism such as, TDDB, HCI, NBTI,EM, four circuit units is designed for reliability test, and they can be embedded into hostcircuit as IP (Intellectual Property) core. The main contents are as follows:(1) First of all, based on the reliability foundation, a solution to the embarrassmentin reliability test in Ultra Deep Sub-Micron regime is developed in this work, which isthe prediction theory of embeddable reliability lifetime prediction units. In addition,described the design concept of the whole reliability prediction system, the predictionscheme aimed to single failure mechanism is achieved.(2) Based on the TDDB failure mechanism, failure models and lifetime distributionof TDDB, this dissertation proposes the design method of TDDB monitor circuit. Basedon the TDDB failure models and the relationship of the monitor circuit and its hostcircuit, equations for prediction circuit design are derived. The monitor circuit istaped-out by Multi Project Wafer in Taiwan Semiconductor Manufacturing CompanyLimited (TSMC)0.18μm CMOS. At last, Parameters for design is obtained byexperiments, and the design method and the monitor circuit is verified.(3) Based on the HCI failure mechanism, this dissertation proposes the designscheme of HCI monitor circuit. The monitor circuit is taped-out by MPW in TSMC0.18μm CMOS. By reliability accelerated lifetime experiments for the HCI monitor circuit and ring oscillators, the design method and the monitor circuit is verified.(4) Based on the NBTI failure mechanism, this dissertation proposes the designscheme of NBTI monitor circuit. The monitor circuit is taped-out by MPW in TSMC0.18μm CMOS. By reliability accelerated lifetime experiments for the NBTI failuremonitor circuit and PMOSFETs, it is proved that the time dependence of the thresholdvoltage shift is typically observed to follow the power-law, and the design method andthe monitor circuit is verified.(5) Based on the EM failure mechanism, this dissertation proposes the designscheme of EM monitor circuit. The monitor circuit is taped-out by MPW in TSMC0.18μm CMOS. By reliability accelerated lifetime experiments for the EM failuremonitor circuit and metal interconnects, the correlative parameters are achieved, and the design method and the monitor circuit is verified.(6) It presents a test access interface based on joint test action group (JTAG) busbecause the reliability failure monitor system presented by this paper would occupy toomuch I/Os. Using JTAG bus as interface of the reliability failure monitor system, it willsave lots of Input/Output resources.In conclusion, the reliability failure monitor system presented by this paper can beembedded into under-test chip, and feedback the real-time degradation of the under-restchip, which isn’t achieved by the traditional reliability analysis and reliabilitysimulation.