Research And Implementation Of Decoding Algorithms For Non-binary LDPC Codes And Three-dimensional TPC Code

Adopting of error-correcting codes in communication systems can effectively improve system reliability.Representatives of the third generation’s forward error correction coding include Low-density Parity-check(LDPC)and Turbo Product Codes(TPC).Compared with binary LDPC,non-binary LDPC(NB-LDPC)constructed in the high-order finite fields can bring greater coding gain,but its algorithm is quite complex and its hardware implementation is difficult.On the contrary,TPC has a fast encoding and decoding speed and relatively simple implementation structure;however,decoding performance is slightly poor.This paper focuses on decoding algorithms and implementation of these two error correction codes.The main contributions are illustrated as follows:First,to further improve the decoding performance of three-dimensional TPC,a new iterative structure is proposed based on the improved serial iterative decoder.In the process of iteration,two-dimensional extrinsic information in the decoder is combined to modify the soft input information of another dimension,and the effectiveness of this method is validated by virtue of simulation.Besides,the decoding performance factors,including the number of iterations,unreliable bits,candidate codewords,and quantized bits,are simulated and analyzed.Secondly,the encoding and decoding algorithms of NB-LDPC codes are studied and analyzed in this paper.Considering the difficulties of hardware implementation,a Quasi-Cyclic LDPC code based on GF(16)is constructed using finite field method.In this process,the system encoding method is used in terms of encoding and extended minimum-sum algorithm with low complexity is adopted in the aspect of decoding.Then,the decoding performance of the system is verified by simulation combined with high-order modulation.This paper also simulates and analyzes the factors that affect decoding performance,including the number of iterations,information truncation,and quantized bits,to determine the appropriate parameter values for hardware implementation.Finally,the NB-LDPC decoder and three-dimensional TPC decoder are implemented on the hardware platform,and each module is designed and simulated.Furthermore,the function of the decoder is verified by comparing the output result of decoder with original transmission bit,and the hardware test of the NB-LDPC decoder is completed on the FPGA board.