Turbo Product Code Technology Research And Its Fpga Implementation

Nowadays, with fast development of the communication technology, how to increase the data rate and improve the quality of the communication system have become the focal problems. Using channel coding technique is one of the effective and economical methods. As a new method of error correction coding, Turbo Product Code(TPC) attracts more attention and can be widely used in many communication fields because of its excellent performance.This thesis makes an analysis of the principle and performance of the Turbo Product Code. Firstly, we discuss the factors which may have effect on the performance of TPC using computer simulation. Then, a parallel algorithm for chase decode, which can be easily implemented based on FPGA by a digital solution, is presented. Based on the above algorithm, design, synthesis and simulation verification of the TPC encoder and decoder have been implemented in the FPGA using Verilog Hardware Description Language. In the end, some programs have been downloaded to a digital receiver for test. The results indicate that this encoder/decoder can accomplish TPC encode and decode for real-time data and the symbol rate can reach 10Mbps. Furthermore, at least 6dB coding gain can be obtained under the condition of 10^-6 BER(Bit Error Rate).The results fully prove the superiority performance of TPC technology. The research results of this thesis can be used in many communication systems of high-data-rate.