Implementation Of LDPC-RS Encoder And Decoder For Non-binary Product Codes

The product code is a channel coding with excellent error correcting performance,which can be used to improve the reliability of the system effectively.However,due to the low speed and high complexity of the hardware implementation for product codes,the important indicators such as the throughput of the codec are affected.Therefore,this thesis researches product codes constructed by low-density parity-check code and reed-solomon code,and further implements the encoder and decoder for non-binary product codes.For the problems of high hardware resources and low throughput,an encoder architecture of non-binary product codes with high throughput is proposed in this thesis.This architecture uses multiple RS encoders and one LDPC encoder in parallel to achieve row encoding and column encoding.Furthermore,the encoding results of multiple RS encoders buffered in the shift registers are transmitted in parallel,and then the double check encoding of the LDPC code is performed.Specifically,the architecture can reduce the encoding latency and improve the throughput by simultaneous working for row and column.In addition,this scheme can reduce the complexity by transmitting the information sequences and column check sequences directly,and the encoder does not need to consume additional memory resources.The test results of the field programmable gate array hardware platform show that the throughput of the LDPC（72,36）-RS（255,251）encoder and LDPC（72,36）-RS（255,247）encoder for non-binary product codes over GF（256）can reach more than 1.2 Gbps.Furthermore,to reduce the resources of LDPC-RS decoder for non-binary product codes over GF（256）,a decoder architecture is implemented in this thesis.Due to the high complexity for the LDPC decoder over GF（256）,one non-binary LDPC decoder is used to process the prior information serially to achieve row decoding.From this,a scheme is used to reduce the hardware resources at the expense of increasing decoding delay,and further reduce the consumption of the decoder for non-binary product codes.The test shows that the LDPC（72,36）-RS（255,251）decoder for non-binary product codes over GF（256）can work at 100 MHz in the Xilinx Virtex6 XC6VLX240T.In addition,compared with the computer simulation,at a bit error rate of approximately 10^-5,the post-simulation results show that the performance loss of the decoder for non-binary product codes is about 0.3 d B.