Research Of SI Model And Simulation Technology For High-speed PCB System

With the rapid development of modern electronic design technology, the electronic system scale has been becoming larger and larger, the speed becoming more and more rapid, the bulk becoming smaller and smaller. And how to solve the signal integrity problem has become one of the key factors in the high-speed digital system design and the high-speed PCB design.In this thesis, we have deeply researched the key factors of the board-level SI issue, the transmission line model and its high frequency effects, the reflection and the cross talk, the framework of the SERDES and the model for the high-speed simulation. After discussing the theoretical method, the vias and the differential vias have been modeled and the simulation results have been analyzed. In order to achieve the balance between the precision and the speed, we combine the electromagnetic field method with the circuit path analysis to simulate the PCB and its feature. In this thesis, the electric circuit model in time domain like I/O Buffer SPICE and IBIS model has been discussed, the electromagnetic field model in the frequency range such as S parameter model of the motherboard connector is also presented. And all the using models have been confirmed through the simulation. As a result of the experiment PCBs, the multi-boards simulation has been built, and the key SERDES networks on PCB have been simulated and analyzed. All of that work is a good explore for high-speed PCB design of key project.The contributions of this thesis include:(1) In view of the stub effect of the via on PCB, the vias and the differential vias in many kinds of structures have been modeled by 3D electromagnetic field full wave simulation tool. The frequency-related characteristic of the vias and the differential vias, as well as the high frequency transmission effects is also analyzed concretely.(2) The mix simulation in time domain has accomplished by using the frequency range model (S parameter model) and I/O Buffer model (SPICE and IBIS), and the time domain simulation result has obtained.(3) The principle and the structure of the SERDES model are researched, and the actual SPICE model of the SERDES as the input/output drivers has been tested in the multi-boards simulation circumstance.(4) By using the test PCBs, multi-board model has been accomplished. The S parameter model for the GBX connector and the difference via has been wrapped and loaded, the multi-boards simulation for 3.125Gbps SERDES buffer is realized.