Research On BCH Encoding And Decoding Of NAND Flash Memor

In the 21 st century,digital integrated circuit technology is constantly developing,and data storage technology,as an important branch of integrated circuit research,is also constantly developing.Among many memories,NAND Flash memory has many advantages such as large storage capacity,fast reading and writing speed,low price,and non-volatile data.It is spread in various fields.However,as the storage capacity of NAND Flash continues to increase,data is stored in the process Errors occur in the process.If these errors are not dealt with,it will cause unpredictable consequences.In order to reduce errors in data storage,some redundant information needs to be added to the stored data,that is,error correction coding.Among many error correction codes,the BCH code is widely used in NAND Flash due to its simple structure,strong error correction capability,and the ability to correct multiple burst errors.Although the BCH codec is added,the reliability of data storage is improved,but the hardware resource overhead is increased.In order to reduce the consumption of BCH codec hardware resources,this article will optimize the BCH codec of NAND Flash.In the BCH codec design,the VHDL hardware description language was used to write,and the Cyclone IV E series EP4CE30F29C6 development board of Altera was selected in the FPGA development software Quartus II 13.0 for verification.In previous studies,the serial encoding was changed to parallel encoding during the design of the BCH encoder,and the parallelism was changed according to the design requirements,which only reduced the calculation time,but did not reduce the complexity of the parallel encoder.This article will use the greedy algorithm to optimize the parallel encoder.After optimization,the lookup table LUT is reduced by 14.03%,and the maximum frequency of the parallel encoding module can reach 371.33 MHz,which effectively reduces the resource consumption of the parallel BCH encoder.In the design of the parallel BCH decoder,part of the finite field constant multiplier in the adjoint module is replaced with a two-choice selector.After the improvement,the LUT of the look-up table is reduced by 5.07%,and the maximum frequency reaches400.8MHz,which is improved compared to the unoptimized one 40.32%.In the error position polynomial module,optimize the IBM algorithm without inversion,which reduces the number of iterations before optimization by half.It only takes 8 iterations to obtain the coefficient of the error position polynomial,and the lookup table LUT is reduced by 44.23%,The register is reduced by 6.01%,and the maximum clock frequency is increased by 8.06%.Finally,for the traditional NAND Flash storage method,a page of data must be read out before it can be decoded.This article adopts a packet decoding method,which can simultaneously read data and decode operations.