Research On SoC Low Power Consumption Method Based On Adaptive Voltage Scaling

With the rapid development of semiconductor manufacturing technology,the characteristic sizes of transistors that make up digital circuit systems are becoming smaller and smaller,and the number of transistors integrated on the same area is increasing by an order of magnitude,leading to an increasing power consumption per unit area of chips and making the energy consumption of chip systems an important factor affecting the development of the semiconductor industry.In order to ensure the normal operation of the circuit system under the influence of factors such as process,voltage,temperature(PVT)deviations,and equipment aging losses,chip designers usually reserve a certain amount of timing margin during the design phase,but this will cause waste of chip power consumption and performance.Adaptive voltage scaling(AVS)technology,as a low-power method that can monitor chip system timing and real-time regulate power supply voltage,can effectively reduce or even eliminate the design margin retained during the design phase,achieving the goal of reducing power consumption from the perspective of reducing the working voltage of the circuit system.Based on the requirement of reducing chip power consumption,this article conducts research on obtaining timing information of critical paths in the chip.An AVS structure based on indirect timing monitoring is designed,and the AXI protocol is used to improve the traditional adaptive voltage scaling bus(AVSBus)to achieve point-to-point communication between the on-chip system and the load point power control device.The main work and innovation of this article are as follows:1.A self-adaptive voltage regulation method based on indirect timing monitoring method is proposed.This article constructs a delay chain through the method of series inverters.Based on the timing analysis of the digital load and inverter delay chain,the length of the delay chain is determined to simulate the delay variation characteristics of the critical path.The length of the timing residual monitoring delay chain is determined by combining AVSBus minimum granularity voltage reading and writing;A lightweight timing monitoring unit is constructed by using triggers.The timing information of the critical path is obtained indirectly by sampling the signal flip at the specific position of the inverter delay chain,which solves the design difficulties and complex structure problems caused by inserting timing monitoring units directly at the end of the critical path.2.Improved traditional adaptive voltage scaling bus with AXI protocol.On the basis of using verilog to implement traditional AVSBus,the AXI protocol is used to convert the interface of AVSBus,and the VALID/READY grip system in the AXI protocol is used to enhance the control of communication between the on-chip system.At the same time,a local register file and a frame structure for transmitting data were designed.Besides,using a 3-bit cyclic redundancy check(CRC)code to verify the transmitted data.The AVSBus slave resynchronization mechanism was used to recover line noise and other error states caused by human factors.3.Functional verification and performance evaluation of the designed AVS system are carried out.A module level verification platform based on the Usual Validation Methodology(UVM)was built,and the functional verification of the design code was completed.A logical synthesis was conducted on the design module based on a certain manufacturer’s 12nm process,with a total comprehensive area cost of 2656.85μm~2.We collected verification test coverage and conducted power analysis on adaptive voltage regulation circuits and digital loads at different operating frequencies using PTPX.When the operating frequency decreased from 1.3GHz to 0.8GHz,a maximum power gain of 53.4% was achieved.