Improved Design Of Timing Monitor And Critical Path Monitoring Point For Adaptive Voltage Scaling

In recent years,with the shrinking size of integrated circuit technology,performance and power consumption are the key factors in the chip design.On the one hand,the traditional circuit designed based on the worst case has reserved more timing margin to ensure that the chip can work in extreme conditions.On the other hand,when working at low voltage,circuit performance becomes more sensitive to variations,including manufacturing variability,voltage and temperature variations,these variations bring a great challenge on integrated circuit design.Adaptive voltage scaling technology based on half-path timing warning monitoring method can effectively restrain variations and reduce circuit power consumption of timing margin by monitoring the timing of path and adjust the supply voltage.This thesis focuses on the design of AVS based on half-path timing warning monitoring method.Monitors are inserted in the half of critical paths in order to monitor the timing of circuit.Low area,low power monitors,the location and quantity of the monitors are the key points in this method.Firstly,two new in-situ data transition monitors are proposed,with small area and wide voltage range working ability.Secondly,the design considers the effectiveness of critical paths in a wide voltage and takes critical paths endpoint registers covering method to select critical paths in all PVT.A algorithm can effectively reduce the number of redundant monitor points.At the same time to ensure that all monitor points in all PVT located after the half critical path point.Thirdly,the monitor system simulation platform and the AVS-C model platform are used to verify the normal and adaptive voltage scaling function of the whole design.Besides,the PCB and the measured platform are designed to analyze the function and power consumption benefit of the chips.Finally,in order to improve the power gain in the normal voltage domain,a deviation adjustment circuit is designed,the on-chip automatic and off-chip manual calibration can be realized.The adaptive voltage scaling technology based on half-path timing warning monitoring method was designed and simulated in SMIC 40nm CMOS technology.The circuit s9234-FIR was taped out.The area of the layout is 1×1.2mm2,where the TDs insertion number is reduced by 3.8 times compared to the tranditional slack-based method with 20%slack Tcycle.The monitor system module area increases by 4.2%.The experimental results show that the base frequency 570MHz for the normal voltage domain,and 10MHz for the low voltage domian.TDs perform well in the range of 0.56V to 1.1V as well as the temperature range of-20??85 ?.The average power consumption benefit of the chip at 0.56V-1.1V changed from 45%to 17%.In the normal voltage domain,supply voltage can be reduced to 1.02V,enabling a maximum 24.18%power consumption benefit.The power saving of the chip can realize a maximum 50.53%in the low voltage when the supply voltage is reduced to 0.49V.As conclusion,this design of half-path timing warning monitoring method can effectively reduce the power consumption.