Two-step ADC Applied In Image Sensors

In CMOS image sensor readout circuit,the column-level Analog to Digital Converter(ADC)has the characteristic that all columns complete analog-to-digital conversion in parallel,and the required speed is low.It is suitable for reading large pixel array.The performance of the column-level ADC determines the frame frequency,area and power consumption of the image sensor.Therefore,the research of high-performance column-level ADC in CMOS image sensor is of great significance.In the column level ADC,single slope ADC has been widely used in CMOS image sensors due to its advantages of simple structure,small area,low power consumption and good linearity.However,the disadvantages of single slope ADC are also very obvious:for N-bit single slope ADC,2~N-1 clock cycles are needed to complete the quantization,the conversion speed is very slow,and the conversion time increases exponentially with the increase of accuracy.In order to solve the problem of slow speed of single slope ADC,this paper adopts the two-step structure combining 1-bit binary search and 11-bit single slope ADC to improve the traditional two-step single slope ADC and proposes an improved 12-bit two-step single slope ADC.Compared with traditional single slope ADC,the quantization cycle is shortened by about 35%and the conversion speed is greatly improved.Compared with traditional two-step monocline ADC,the proposed ADC avoids quantization dead band.The main research contents of this paper include:In this paper,the traditional two-step single slope ADC circuit structure and timing control are improved.The ramp signal is always connected to the lower plate of the hold capacitor,which stabilizes the voltage of the lower plate,prevents charge sharing between the parasitic capacitor and the hold capacitor,and avoids quantization dead band.The reference voltage in the coarse quantization stage is independent of the charging voltage of the holding capacitor.By setting the charging voltage less than the reference voltage,the slope overlapping design is realized to avoid the quantization dead band caused by the comparator judgment error in the coarse quantization stage.The coarse quantization result is used as the marker bit of the complement code.After the quantization,it is decided whether to complement the quantization result according to the marker bit to make the quantization result more accurate.The key modules are designed in this paper.The offset memory circuit is designed to calibrate the offset voltage of the comparator to prevent the random deviation of the quantization results of ADC caused by the offset voltage between the columns.The slope generation circuit uses the wide swing common source common gate current mirror as the current source to charge the capacitor,so that the slope signal has a larger swing and a more stable slope.D flip-flop serial connection is used to form a counter,through the control signal can realize the functions of clearing,addition and subtraction counting.In this paper,the key modules and the overall circuit of the ADC are simulated based on Cadence using 0.18μm 1P4M CMOS process.Under the condition of 600MHZ clock frequency and single edge counting,the quantization period of ADC is about 6.167μs.Under the condition of 3.3V analog power supply voltage and 1.8V digital power supply voltage,the average power consumption of ADC in this paper is the largest at process corner FF,which is about 121.09μW.