Design Of The ESD And Surge Protection For RS485 Chip With Serial Communication Interface

The RS485 chips with serial communication interface are widely used for signal acquisition and data interchange.Due to the high data rate and low cost,the RS485 chips are highly favored in the fields of communication engineering such as automotive electronics,smart grid and aerospace.In order to improve the accuracy and stability of data transmission,the RS485 chips are highly required for strong electrostatic discharge(ESD)and surge protection capability.At present,typical ESD/surge protection products in the market are generally limited by the large area,low energy efficiency and unexpected parasitic effects,which are becoming major constraints to the development of RS485 chips.Therefore,by utiliazing high-integrated ESD/surge protection design methods,this dissertation proposes a serial of novel protection strategies combing circuits and layouts to meet the ESD/surge protection requirements of RS485 chips.The physical mechanism of the protection strategies are deeply discussed by the Sentaurus simulation tools.The working mechanism and electrical characteristics of the proposed strategies are analyzed and verified by the testing systems,such as Transmission Line Pulse Test(TLP).The main research contents of the dissertation are as follows:Firstly,the dissertation briefly describes the circuit composition and working principle of the RS485 chips.The relevant physical models and testing techniques of ESD/surge protection designing are explained,the protection design window and key parameters are summarized,and the operating process of the simulation tool Sentaurus is introduced.Moreover,the working mechanism of the conventional protection strategies for RS485 chips are analyzed and discussed by Sentaurus simulation,such as resistors,capacitors,transistors,metal-oxide-semiconductor field effect transistors(MOS),and silicon controlled rectifiers(SCR).Secondly,aiming to the on-chip ESD protection requirements for the enable port of RS485chips,a series of the experimental devices,including dual MOS auxiliary triggered SCR(PNMSCR)and the GGNMOS are proposed and fabricated.By Sentaurus simulation and TLP test,results show that current discharge efficiency per unit area of PNMSCR is increased by 130%,due to the internal SCR.Furthermore,the holding voltage of PNMSCR is elevated from 5.2 V to 7.1V,because of the paralleled PMOS and the segmentation doping region.The snapback margin of PNMSCR is well matched with the ESD protection designing window of the enable port.Aiming to the ESD protection requirements for input/output port of RS485 chips,a dual directional protection solution with high holding voltage(HVNSCR)is proposed.The HVNSCR is achieved by embedding the multi-Darlington transistor and the high-current-gain NPN transistor into SCR.The snapback margin of HVNSCR is controlled within 2 V,enhancing the anti latch-up ability effectively.Thirdly,focusing on the ESD protection requirements for the multi-power domains in RS485chips,a dual directional protection solution with low trigger voltage(DDTSCR)is proposed.The trigger voltage of DDTSCR is reduced into 1.7 V by introducing a diode string path into SCR.And the high current discharging capability of 4.2 m A/μm~2is harvested due to intrinsic SCR.In addition,this dissertation proposes a modified high voltage MOS with strong anti-ESD capability by introducing SCR path.Finally,in order to meet the off-chip surge protection requirements of the input/output port in RS485,a dual-directional zener diode triggered SCR(DZSCR)is proposed.The TLP tested results shows that the DZSCR possesses a high secondary failure current of 5.8 A.The snapback margin of DZSCR can meet the design window of the input/output port by 3 cascaded connections.And the anti-surge ability of the DZCSR can be achieved by 8 fingers-like connections.Aiming at the surge protection requirements of RS485 power rails,an area-efficiency high-gain SCR(AESCR)is proposed.The AESCR achieves a strong surge current discharge capability of 1.3 m A/μm~2 with a small layout area of 900μm~2by using layout design technology.Moreover,the protection capability of the AESCR can be further improved by multi-fingers designing.