Design And Implementation Of 5G PUSCH Channel Error Correction Processor

With the continuous development of 5G communication technology,various mobile communication standards are also being rapidly updated,and mobile devices have higher and higher requirements for data throughput,reliability,and flexibility of baseband processing.5G base stations need to complete high-throughput data processing work under the constraints of low power consumption and area,and also need to flexibly support multiple protocols,which makes the research of multi-mode forward error correction processors of great significance.Based on the existing research results of this topic: TASIP and QASIP,this paper mainly realizes the following innovations and expansions:1.The PUSCH channel coding standard under the 5G NR standard is studied,and the LDPC decoding function of 2 base maps 8 index and 51 expansion factors that meet the 5G standard is added to the original design,so that the forward error correction processor design proposed in this paper is Compatible with mainstream communication standards such as WIFI,3GPP-LTE,5G NR;2.This paper adopts the design methodology of Application Specific Instruction-set Processor(ASIP)and the Single Instruction Multiple Data(SIMD)architecture to expand the parallelism of this design,making it have up to 48 At the same time,this paper studies the elimination of RAW conflicts in the operation path,so that the decoder obtains high throughput and adapts to more communication scenarios;3.This paper replaces the memory frequency multiplication requirement in the original design through the research and redesign of the memory subsystem.Since SRAM cannot be decomposed by Pipeline,this design doubles the system operating frequency limit,which is beneficial to improving throughput,Area efficiency and system power consumption are of great significance.Finally,our design achieves a maximum QC-LDPC decoding throughput of 5293.78 Mbps compared to the TASIP design with the highest QC-LDPC decoding throughput of 533 Mbps(12 SISOs running in parallel at 200 MHz memory clock frequency of 400MHz)(48 parallel SISO)when the system frequency is 400MHz(the memory clock frequency is also 400MHz).Through further circuit optimization,the upper limit of the system clock is raised to 1.1GHz.We finally delivering up to 1.95 G throughput for WLAN,2.93 G for WiMAX,and 11.65 Gbps for 5G NR.Finally,the design is physically verified through logic synthesis using a 28 nm SMIC CMOS cell library with a core area of 0.86mm2 and a reported logic gate count of 1716 K.We developed a processor simulator,configurator,assembler,and hardware RTL code,etc.,and performed functional verification using Modelsim and physical verification of the processor using Design Compiler and Innovus.