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Design Of Video Deinterlacing System Based On FPGA

Posted on:2023-06-27Degree:MasterType:Thesis
Country:ChinaCandidate:S Z FuFull Text:PDF
GTID:2558307163489564Subject:Electronic and communication engineering
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With the development of science and technology,digital TV is gradually popularized,and analog signals are gradually replaced by digital signals.my country’s TV broadcasting system standard adopts the Pal system(Phase Alternative Line,referred to as PAL),and the PAL system is an interlaced scanning method.In order for users to get a better visual perception,before the interlaced video is transmitted to the digital device,the interlaced video should be converted into a progressive video to avoid blurring,jaggedness,interline flickering and other problems when the interlaced video is displayed on the digital device,which affects people’s Therefore,de-interlacing processing has become an essential operation of modern digital display devices.Compared with the traditional way of using digital signal processing technology(Digital Signal Processing,referred to as DSP)to realize de-interlacing operation,Field Programmable Gate Array(Field Programmable Gate Array,referred to as FPGA)with rich internal resources and fast data processing is used in video images.Handling is more advantageous.This paper first carefully studies different types of deinterlacing algorithms at home and abroad,and compares and analyzes them.On the basis of the existing deinterlacing algorithms,certain improvements are made,and a deinterlacing algorithm suitable for FPGA implementation is proposed.Interlacing algorithm,and for this algorithm,the specific implementation and verification are made on FPGA.In this paper,based on the traditional edge average interpolation algorithm,combined with the motion-adaptive de-interlacing algorithm,the motion detection method of 4-field difference is used to obtain the motion state of the pixels on the interlaced image.The static area adopts the median filtering deinterlacing algorithm,and the moving area adopts the improved edge average interpolation deinterlacing algorithm,and finally obtains the pixel points to be interpolated,so that the interlaced video is converted into a progressive video.In the process of video de-interlacing,due to the huge amount of data and limited internal resources of FPGA,DDR3 SDRAM off-chip memory is used to store video data.Finally,the result processed by FPGA is displayed on the LCD in real time.Finally,the image quality after de-interlacing is analyzed subjectively and objectively.Subjectively,by directly observing the deinterlaced image on the display,there is no blur,jaggedness and other undesirable phenomena in the video image;objectively,for the progressive video image processed by several different deinterlacing algorithms,the peak signal-to-noise ratio(Peak Signal-to-Noise Ratio(PSNR for short)and Structural Similarity Index Measure(SSIM for short)are compared.The results show that the algorithm in this paper is the best,and it proves that the proposed algorithm based on FPGA video Rationality,reliability and superiority of deinterlacing solutions.
Keywords/Search Tags:de-interlacing, FPGA, motion detection, DDR3 SDRAM
PDF Full Text Request
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