Research And Design Of High Speed CMOS＿SubLVDS Transceiver Circuit

Recent growth in high-end processors,multi-media,virtual reality and networking has demanded more bandwidth than ever before.Some of today’s biggest challenges that remain to be solved include: the ability to transfer data fast,lower power systems than currently available,and economical solutions to overcome the physical layer bottleneck.Previous data transmission standards all have their own limitations most notably in transferring raw data across a media.Low Voltage Differential Signaling(LVDS)is a high speed(>155.5 Mbps),low power general purpose interface standard that solves the bottleneck problems while servicing a wide range of application areas.Based on a comprehensive analysis of the current research status in this field at home and abroad,this thesis designs an ultra-low voltage differential signal high-speed transceiver interface circuit based on the ANSI/TIA/EIA-644 A protocol standard for low voltage standards.The overall circuit of the high-speed SubLVDS driver consists of a single-ended-to-differential signal circuit,a pre-emphasis circuit,a common-mode feedback circuit and a low-voltage bandgap reference source circuit.Among them,the single-ended to differential circuit adopts a skew-free design,which effectively improves the negative impact of skew on the circuit performance.The pre-emphasis circuit uses an additional pre-emphasis current source in the core circuit to compensate for the high-frequency components,which turns on when the transmitted signal is flipped and turns off when it is stable,significantly reducing power consumption and improving the signal quality.The common mode feedback circuit optimizes the compensation structure and adopts a dual current source design with Miller compensation to monitor and reverse the output common mode level in real time;the low-voltage bandgap reference circuit with resistive interpolation provides a stable zero-temperature coefficient common mode level.The overall circuit of the high-speed SubLVDS receiver designed in this thesis consists of a rail-to-rail preamplifier circuit,a hysteresis comparator circuit,and a shaping buffer circuit.The rail-to-rail preamplifier circuit enables rail-to-rail common-mode input range and optimizes the current selection module to reduce power consumption;the hysteresis comparator circuit suppresses false flip-flops caused by noisy signals;and the shaping buffer circuit effectively improves the output drive capability and shapes the signal.This thesis designs a SubLVDS transceiver circuit based on the Towerjazz 0.18μm standard CMOS process,and performs circuit simulation and layout implementation under different environments and process corners.The results show that the transmitter circuit can convert a CMOS single-ended signal with an input rate of 1Gbps into a differential signal with a swing of 150 m V,and the output common-mode level is maintained at 0.9V,which can drive a 5p F capacitive load.The receiver can stably receive the incoming 1Gbps differential signal and reduce it to the system’s internal CMOS single-ended signal.the simulated analog waveform output of the SubLVDS transceiver circuit is stable and the data is correct.the overall circuit power consumption is about 15 m W,which meets the design specifications.