Design Of Power Supply System For DSP Chips In Multiple Power Domains

Due to the continuous progress of integrated circuit technology,various digital signal processors(DSP)appear.Power supply system is indispensable to DSP chip,and its performance has a direct impact on the real-time processing ability of DSP chip.There are three typical types of power supply system,namely low dropout linear regulator,charge pump and switching regulator.Among them,LDO ripple is small,there are few peripheral devices and low cost,which meets the requirements of DSP power supply system.Because many functional modules are integrated into the DSP chip,a multi power domain DSP chip power supply system is needed.Firstly,this thesis analyzes the index requirements of multi power domain DSP chip power supply system.Because it has both digital and analog circuit modules,digital ground and analog ground isolation technology is adopted to isolate the influence of digital substrate noise on analog circuit.Among them,3 V LDO and 1.2V LDO provide power supply voltage for analog interface amplifier,operational amplifier,analog comparator and analog-to-digital converter.According to the design index,LDO with external capacitor is adopted for design.The adjustment tube adopts PMOS tube,and the error amplifier adopts the folded cascode structure with PMOS tube current mirror as the load,and a primary buffer stage is added.One low-frequency secondary pole is divided into two high-frequency secondary poles to improve its stability.1.7 V LDO provides power supply voltage for the core,PLL and oscillator.According to the design index,LDO without external capacitor is adopted for design.NMOS transistor is used as the regulator,and the folded cascode structure with NMOS transistor current mirror as the load is used as the error amplifier,and zero pole dynamic compensation circuit is added to improve the stability of LDO.This design is based on UMC 55 nm CMOS process,and the circuit design is completed under cadence platform.At 1 KHz,the power supply voltage rejection ratio is greater than – 60 dB,the temperature drift is less than 50 ppm in-40 ℃ ～ 125 ℃,the output ripple of LDO is less than 100 mV,and the linear adjustment rate and load adjustment rate are less than 1%.Good performance and meet the design requirements.