FPGA-Based Design And Implementation Of Anti-Burst Error Coding Scheme For PPM4 Free Space Optical Communication Systems

Free-space optical communication systems are widely used in the field of wireless communication due to the advantages of low power consumption,high transmission security,high bit rate,easy installation,and license-free communication.For the space optical communication system between the satellite and the ground,it is easily affected by atmospheric turbulence and extreme weather such as rain,snow,fog,haze,etc.,causing communication interruptions,resulting in sudden errors in data transmission.In this paper,an anti-burst error coding scheme combining forward error correction and interleaving is designed to reduce the impact of burst errors on communication quality effected by communication interruptions caused by extreme weather and atmospheric turbulence.The main contents of the research work are as follows.1.An anti-burst error coding scheme based on the combination of RS code and interleaving is designed and implemented,and a real-time verification system of 1Mbps indoor free space optical communication is built.The experimental results show that the designed scheme can effectively correct burst errors of 100ms duration.The system receiver sensitivity is improved by 8.55dB@1E-6.At the same time,the free space optical communication real-time experimental system of 6.5 kilometers and 13.9 kilometers in the field has been completed.The results show that:under the weak turbulent channel,the number of interruptions per unit time of the proposed scheme is reduced by more than 70%,and the system bit error rate is reduced from 1E-4 to 1E-7 and below.2.An anti-burst error coding scheme combining LDPC(Low Density Parity Check)code and interleaving is designed.A simulation platform including a burst error channel model is built.The simulation results show that in the PPM4(Pulse Phase Modulation 4)system with a line rate of 20Mbps,the proposed scheme can correct burst errors with a duration of 10ms,and the system bit error rate is lower than 1E-6.3.Complete the FPGA design and implementation of the LDPC decoding,interleaving/de-interleaving sub-modules in the above scheme.The interleaving module at the transmitter occupies 4Mbit of hardware resources of the storage module,and the receiver is 24Mbit.The functional simulation verification results show that the proposed scheme can correct burst errors of 10ms duration in a PPM4 system with a line rate of 20Mbps.