Design Of LDPC Codes And The FPGA Implementation In Burst Communication

In recent years,with the rapid development of electronic technology,many traditional science and technology have also made great progress.In the field of electronic communication,the rapid development of digital chip makes the size of communication equipment gradually decrease,but its functions are gradually increasing.With the increasing integration of integrated circuits,more and more resources can be used on chips of the same size.At the same time,due to the improvement of technologies and materials,the frequency of chips is higher and higher when they work stably,while their power consumption is constantly reduced.Therefore,the digital chip will have the broad application prospect in both the military and the civil fields.In the field of military communication,in order to solve the problem of communication among a variety of military radio,the United States has launched the "Speakeasy" project in the 1990 s.It was based on the concept of Software Defined Radio to realize military radio equipment communication modules in the system by software as far as possible,which largely increases the flexibility and versatility of the equipment,and all of this depends on the Field Programmable Gate Array(FPGA)chip.Burst communication is a kind of wireless communication in which the original information is transmitted centrally at a very high data transmission rate at random moments.On the one hand,with the high data transmission rate,the signal duration is short,and the information carried in each burst communication is little.On the other hand,the time of each burst communication is not constant,which makes the signal unpredictability in the time domain and has certain anti-interception characteristic.In this thesis,on the basis of the laboratory project,the LDPC code for burst communication is designed,and the corresponding encoder and decoder are designed on FPGA hardware platform to meet the engineering requirements.The main content of this thesis is as follows:1.LDPC code has important research significance as a good code whose performance is close to shannon's limit.The definition of LDPC code is explained by combining with Tanner diagram.On this basis,several relevant encoding and decoding methods are introduced.2.Several common methods for LDPC code construction are introduced.After analysis,this thesis uses the construction method which based on Cyclic Permutation Matrix to design the required codes to meet the needs of the project.3.According to the project requirements,LDPC encoder and decoder are designed reasonably.In order to meet the real-time decoding requirement of the project,the decoder of LDPC code employs parallel structure for iterative decoding.On the FPGA hardware platform,the encoder and decoder are implemented and tested.Simulation and board-level verification results show that the LDPC encoder and decoder designed in this thesis works well and meets the design indexes.