Peripheral Circuit And Parallel Computing Design Of Memory-Computing Integrated Chip Based On RRAM

In the past ten years,with the rapid progress of deep convolutional neural network algorithms,neural network applications such as visual perception,speech recognition,and automatic driving have been greatly developed.The data associated with these emerging information technologies presents three significant new features:Large data volume,diversity of data types and real-time processing.When using the new computer storage-computing integrated architecture for convolutional neural network computing,there is no need to frequently transport computing data between the logical computing unit and the data storage unit,which greatly reduces the computing delay and computing power consumption of neural network computing.It has great application prospects.Resistive Random Access Memory(RRAM),as a new type of non-volatile memory,has the advantages of simple structure,high integration,low power consumption for reading and writing,and good logic computing performance.RRAM is considered to be an important hardware for realizing the memory-computing integrated architecture.In this thesis,an RRAM memory-computing integrated chip for neural network computing in edge devices is designed.Compared with the existing embedded general-purpose MCU chips,the computing energy consumption ratio is improved by more than 10 times,and it has a good application prospects in edge devices.This thesis completes the design of a RRAM memory chip based on the Serial Peripheral interface(SPI)protocol,with a storage capacity of 1 Mb and a rated operating frequency of 10 MHz.Then,the peripheral circuit and control circuit for convolutional neural network calculation are designed in the memory to realize the convolutional neural network calculation and complete the MNIST handwritten digit recognition application.This research work can be divided into the following parts:(1)This thesis designs RRAM multi-level storage array and convolutional neural network parameter storage scheme.In this thesis,we research the basic principles of RRAM devices and storage arrays,use 1T1R architecture to design RRAM multi-level storage arrays,and use Verilog for behavioral modeling.This thesis conducts research on convolutional computing kernels fabricated in RRAM memory arrays,and designs the storage scheme of convolutional network parameters in the RRAM storage array.(2)This thesis designs the overall architecture and peripheral circuits of the RRAM memory-computing integrated chip.According to the design principle of non-volatile memory,the interface protocol,instruction set and working status register of RRAM chip are designed.This thesis designs row and column address decoding circuit,data buffer circuit,sensing data circuit and reference array on the basis of memory peripheral circuit.Based on analyzing the principle of convolutional neural network calculation,this thesis designs input mapping circuit and Re LU activation for convolutional neural network calculation circuit and max pooling circuit.(3)This thesis designs the control circuit that realizes the read-write function and the calculation function.The RRAM memory and computing integrated chip is designed to read and write instructions and read and write control circuits,and the write instructions are used to complete the storage of neural network parameters.Using RRAM storage and computing integrated chip to complete MNIST handwritten digit recognition application.Compared with the serial convolutional neural network computing scheme,this thesis designs a parallel computing scheme to accelerate neural network computing,and designs a parallel computing control circuit to complete the parallel convolutional neural network calculation.This scheme obtains a 2.3 times increase in computing speed,and reduces data cache resource requirements by 22.7 times.(4)The function verification of the RRAM storage and computing integrated chip designed in this thesis is carried out,and the logic synthesis of the peripheral circuit and the control circuit is carried out.This thesis uses VCS and DVE software to simulate the read-write function and calculation function,verify the correct function of the peripheral circuit and the control circuit,and verify that the calculation result is correct,and can complete the MNIST handwritten digit recognition task.Based on the TSMC 130 nm process library,this thesis uses the logic synthesis software DC to synthesize the designed RTL-level peripheral circuits and control circuits,and verify that the designed circuit meets the operating frequency of 10MHz.The integrated circuit area is 45123.45μm~2,and the power consumption is 46.5673μW.