The Novel Structure Design And Simulation Of Tunnel FET

As complementary metal-oxide-semiconductor (CMOS) is aggressively being scaled down, it faces the fundamental limitation that the subthreshold slope cannot be further reduced below 60mV/decade at room temperature. Recently, a group of novel devices with the super-steep SS aroused great interests in the research community as it can potentially replace the metal-oxide-semiconductor field effect transistor (MOSFET) for low power applications. Among the device candidates, the tunneling field effect transistor (TFET) is the most promising one due to its excellent switching characteristics and the good compatibility with the current MOSFET platform. One of the technical challenges of the state-of-the-art TFET technology is the low drive current, which may hinder its widespread application. For serving as ideal switching devices in future ultra-low power applications, scaling down the TFET lengths is essential to follow the pace of Si-based CMOS technologies. However, the short channel effect is the major concerns to reduce the device lengths while retaining favorable on-off switching characteristics. Although some approaches can offer a stronger gate control to salvage TFETs partly from the short-channel effects, scaling TFETs into the sub-20 nm regimes is still a considerable challenge because of the presence of direct source-to-drain tunneling and the penetration of lateral electrical field.The main work of this paper is structure design and optimization of TFETs to improve the drive current and explores the proper device design of extremely scaled TFETs without short-channel effects.First, a novel asymmetric dual-gate tunneling FET (ADG-TFET) is proposed and investigated. ADG-TFET has shown tremendous potential as it combines advantages of TFET,which has low subthreshold slope, and JLFET, which has high ON-state current. Our simulated ADG-TFET shows both high ON-state current and low subthreshold slope.Then, an improved trench single gate tunneling field effect transistor (TSG-TFET) is investigated. With ultrathin channel, the device can increase the gate controllability for enhancement of tunneling current. The drain-source leakage current is suppressed by the introduction of an intrinsic region at the drain, reducing the electric field and enlarging the tunneling barrier width along tunneling path at the tunnel junction in the OFF-state. For the short-channel TFET, it is expected that the proposed TSG-TFET have strong immunity to short-channel effects.Finally, a Tunnel Field-Effect Transistor with asymmetric Schottky-junction drain(ASD-TFET) is designed and investigated. ASD-TFET contains a conventional p-n junction at the source side and Schottky contact at the drain side,At the Schottky-junction drain side,the sufficiently large tunneling barrier with low electric field significantly suppresses the electron to tunnel from the valence band of source to the drain. To scale TFETs into sub-10-nm regimes, the proposed ASD-TFET has significantly stronger immunity to short-channel effects.