Logic Design And Implementation Of Sequencer With 5GSPS Sampling Rate

Arbitrary waveform generator can simulate complex signals in test.In order to improve the complexity of the signal,the high-performance arbitrary waveform generator generally uses the sequence synthesis technique which equivalently increases the storage depth.Through the orderly combination of characteristic waveform segments,the defect that the samples of complex waveform is much larger than the capacity of waveform memory is effectively solved.However,with the increasing demand for the bandwidth and complexity of analog signals in arbitrary waveform generators,the sequence synthesis method based on register architecture has become an important factor restricting the sampling rate and output signals' complexity of the sequence synthesis module,due to low address generation efficiency and poor functional scalability which is caused by the close coupling structure between the address generator and the sequence generator.In view of the above problems,this thesis aims to improve sequence signals' complexity and solve the contradiction between sampling rate and sequence generator efficiency and studies high-speed sequence synthesis technique,finally realize sequence and scenario synthesis at 5GSPS sampling rate.The main research contents are as follows:1.Research on high-speed sequence / scenario synthesis technique.In response to the problems of structural design coupling caused by the original sequence synthesis method using register architecture,the sequence synthesis method based on instruction set architecture is studied.This architecture integrates sequence parameters such as waveform segment length and repetition frequency into waveform segment synthesis instructions,uses instruction processor to parse the instructions,and schedules the address generation and data reading operations by time sharing,which can improve the working efficiency of the address generator.Aiming at the problem of limited depth expansion of single-layer sequence storage,the scenario synthesis method is studied.By adding sequence jump instructions integrated with scenario parameters in the instruction set,the jump output of waveform segment/sequence is realized and the complexity of the sequence is improved.2.Logic design of sequence synthesis module.Combined with the hardware platform architecture of '' FPGA + SDRAM + DAC '',the logic circuit design of sequence/scenario synthesis processor and waveform data processing module is completed.The sequence/ scenario synthesis processor replaces the sequence generator and uses a state machine to read,parse and execute the waveform segment synthesis instructions and sequence jump instructions in the instruction set to achieve the jump or repeat output of DDR3 SDRAM addresses,where the address generation efficiency is greater than the average data transfer rate of 5GSPS.The sequence parameters are converted into descriptors and sent to the AXI DMA IP core working in SG mode,where the read data rate meets the 5GSPS sample rate data transfer rate requirement.In terms of data processing,the sampling rate range is expanded to 300SPS?5GSPS by reducing the data rate.The state machine is used to convert the trigger function into waveform start/stop output operations,and then three trigger output modes,such as gated,single and continuous trigger,are achieved to enrich the control function of the sequence synthesis module.The test results show that the designed sequence synthesis module can realize arbitrary waveform/sequence/scenario signals output with 1?65535 repetitions,where the length of wavefrom segments is 1600?4G;and meanwhile the module has control fuctions such as sequence triggering and dynamic sequence control.The designed sequence synthesis module is at the same level of sequence function as Tektronix AWG5200 AWG products.