Design Of High Speed And Complex Sequence Waveform Generation Module Based On Hybrid Storage Architecture

In addition to generating standard function waveforms such as sine and triangle waveforms,the Arbitrary Waveform Generator(AWG)can also use waveform editing software to simulate the signal details accurately in the test equipments to achieve accurate signal reproduction and it is widely used in electronic testing equipments such as Automatic Test Equipment(ATE).With the increase in the complexity and diversification of test scenarios in fields such as ATE,how to increase the number of test vectors in the arbitrary waveform generator has become a current research difficulty.A test vector is a collection of waveform segments,which is also called a sequence waveform in AWG.Sequence synthesis is a method of generating sequence waveforms in AWG.This architecture realizes the generation of sequence waveforms by reading sequence instructions and orderly combining the waveform segments in the memory.However,the traditional sequence synthesis architecture has the defect that the limited storage capacity of the instruction memory is difficult to meet the sharp increase in parameters such as the bit width of the sequence instruction and the number of sequence waveform outputs in practical applications.This thesis proposes an improved scheme based on a hybrid storage architecture to solve this problem.By mixing waveform data and sequence instructions in a large-capacity dynamic memory,the capacity limit of the instruction memory is broken,thereby increasing the number of sequence waveform outputs.To improve the performance of instruction reading and execution under the hybrid storage architecture,this thesis analyzes and provides some improvement methods.The main research contents of this thesis are as follows:1.Research on sequence synthesis architecture based on hybrid storage mode.This thesis introduces the sequence synthesis method based on the hybrid storage mode,and then analyzes its and the traditional sequence synthesis architecture in increasing the sampling rate and the number of sequence output numbers.By modeling parameters such as sample rate,minimum waveform length and instructions read delay,it is pointed out that although the hybrid storage architecture of this thesis has met the requirements of the minimum waveform segment length,there is also the problem of excessive delay in reading sequence instructions from dynamic memory and long instruction execution time.2.Research on methods to reduce the delay in reading sequence instructions.In view of the high latency of reading sequence instructions in the hybrid storage structure,this thesis adopts a sequence instruction Cache with a direct mapping structure.The instructions read delay is reduced from 68 clock cycles to 3 clock cycles by pre-storing512 sequence instructions in it.3.Research on methods to reduce the execution time of sequence instructions.The instruction execution method based on the prefetch mechanism was proposed,aiming at the problem of long instruction execution time in the hybrid storage structure.By advancing the read instruction enable signal by 5 clock cycles,the interval for reading instructions is reduced from 23 clock cycles in the traditional architecture to 11 clock cycles in the scenario of all waveform segment instructions appear continuously and hit in the Cache.The test results show that the output capacity of the theoretical maximum number of sequence waveforms based on the hybrid memory sequence synthesis architecture designed in this thesis has reached 10~8,which exceeds the indicators of similar instruments at home and abroad such as Keysight M8190A.