Design Of The Data Generation Module Of The 4GSPS Arbitrary Waveform Generator

Arbitrary waveform generator,which is based on direct digital synthesis technique,develops rapidly in recent years.It can generate user-defined complex waveforms with high frequency resolution and frequency stability,so it is widely used in the field of electronic testing.With the development of electronic technology,test task needs stimulation signals to have higher frequency and more complex details to simulate signals in true environment.The sampling rate and storage depth are two key specifications for arbitrary waveform generators,which determine the quality of the output signal.Therefore,the research of increasing the sampling rate and storage depth has become a hotspot and also a difficult in the study of arbitrary waveform generator.In order to increase the sampling rate and storage depth,the design of the data generation module of the generator which based on the project of "4GSPS arbitrary waveform generator" is mainly discussed in this thesis.With the functions of storing the desired waveform data and generating target waveform data in high-speed during waveform synthesis,data generation module is a key design which determines the sampling rate and the waveform storage depth of the arbitrary waveform generator directly.Works done in this thesis are as follows:(1)Design of high-speed and deep storage waveform look-up Table.The feasibility of using DDR3 SDRAM as the waveform look-up table is discussed in this thesis.Besides,some methods are proposed to solve problems such as the instability of the memory reading efficiency.Designs such as clock domain crossing cache,high-speed memory control logic in the FPGA are given.Finally the design of look-up table realized sampling rate of 4GSPS,and storage depth of 2G points.(2)To solve the problem of low utilization efficiency of storage space when generate a complex long period signal,the principle and scheme of sequence synthesis is analyzed.According to the addressing characteristics of DDR3 SDRAM,a kind of address generator design by using instruction mode is proposed.With the ability of addressing in a quick and flexible way,the address generator realized sequence waveform synthesis with maximum segment length of 64 M points and the number of segment repetitions from 1 time to 616?10 times.(3)Testing and verification.According to corresponding functions and specifications,the test scheme is set up and the test platform is built.Through analyzing the test results,it is proved that the data generation module realized all the design targets: it realized standard waveforms and arbitrary waveforms synthesis with maximum 2G points length and highest 4GSPS sampling rate;it had the ability to receive trigger signal and realized the trigger delay function;the module realized sequence waveform synthesis under specified parameters.