Hardware Design And Implementation Of Dual Channel Arbitrary Waveform Synthesizer With 10GSPS

In order to meet the increasingly high test requirements of various industries,arbitrary waveform generator is developing towards the direction of high sampling rate,deep storage and precise channel synchronization.This thesis aims at the hardware design of 10 GSPS dual-channel arbitrary waveform synthesis module,and focuses on solving the technical problems of high-speed large capacity storage,high-speed data transmission interface synchronization and broadband high resolution clock synthesis.The main work includes the following:In order to meet the increasingly high test requirements of various industries,arbitrary waveform generator is developing towards the direction of high sampling rate,deep storage and precise channel synchronization.This thesis aims at the hardware design of 10 GSPS dual-channel arbitrary waveform synthesis module,and focuses on solving the technical problems of high-speed large capacity storage,high-speed data transmission interface synchronization and broadband high resolution clock synthesis.The main work includes the following:1.Overall scheme design.By analyzing the access characteristics of DDFS and DDWS waveform synthesis technology to memory,combining with the storage requirements of each channel of 4G sample point of this project,and on the basis of comparing various memory performance,DDWS is selected to realize waveform synthesis,and the system framework of "FPGA+DDR3 SDRAM+DAC" is determined.To meet the requirements of broadband and high resolution sampling clock,the clock synthesis method of DDS excitation PLL is adopted to achieve the target requirements of2.5GHz ? 5.0GHz frequency range and 100 Hz resolution.To solve the problem of complex read/write control and data reading discontinuity of DDR3 SDRAM,a data reading and processing scheme combining IP core and asynchronous FIFO with memory interface control is adopted to process the output of DDR3 SDRAM into uniform,continuous and controllable data flow.Aiming at the requirement of ±25ps synchronization accuracy at 10 GSPS sampling rate,the synchronization requirement of multiple JESD204 B DAC interface was analyzed,and a DAC synchronization scheme based on JESD204 B deterministic delay was designed.Aiming at the requirements of precise delay and large dynamic adjustment range,a channel timing scheme based on coarse and sampling clock fine-tuning of waveform data points was designed to achieve the requirements of 250 fs delay stepping and ±2ns delay range.Aiming at the synthesis and conditioning of 400 ps pulse width and synchronous marker signal,a data marker synthesis method with the same origin as waveform data source was selected to synthesize marker signal,and a high-speed signal conditioning scheme of "delay line + Pin Driver" was designed.2.JESD204 B key link parameters are calculated according to 12.5Gbps channel rate,and the design of receiving and sending circuit between DAC--AD9166 and FPGA--XCKU060 is completed.Through the fanout HMC7044 synthesizing DAC synchronization required key clock,and equal length distribution to two DAC and FPGA;By using jitter attenuator Si5319 and PLL chip ADF4355,a sampling clock with a resolution of less than 100 Hz and a resolution of 2.5GHz ? 5.0GHz is obtained by 200 frequency doubling of the output of 12.5MHz ? 25 MHz of DDS chip AD9954.Through the delay function of HMC7044 and the delay line HMC911,the 250 fs delay fine tuning of sampling clock within 25 ps is realized.Through the high-speed pin driver ADATE209 and delay line SY100EP196 V,the amplitude control of marker signal from-0.5V to 1.7V,delay range of ±2ns and synchronization deviation of ±25ps are realized respectively.Test and verification showed that the designed waveform synthesis module had the sampling rate of 10 GSPS,the storage depth of 4G samples per channel,the synchronization deviation was less than 25 ps,the delay range of ±2ns and the adjustment accuracy of 250 FS.The marker signal reaches 400 ps pulse width,-0.5V?1.7V output amplitude,delay range of ±2ns and synchronization deviation of ±25ps.