Research On Key Technologies Of P-Channel NexFET Structure Devices

As a new type of power MOSFET device,NexFET device has the advantages of low on-resistance,low gate parasitic effect,high reliability,high current density and large current capability,and the process is simple and easy to implement.However,due to the large output capacitance of the NexFET device structure,the output efficiency of the device is reduced,so how to reduce the output capacitance of the NexFET device has become one of the research directions of the NexFET device in this thesis.At the same time,under the background of the continuous development of power semiconductor devices,the market has stricter and stricter requirements on the reliability of NexFET devices.Therefore,how to further reduce the surface electric field strength of NexFET devices and improve device reliability has also become the focus of this thesis.Based on this,this thesis designs a 20 V P-channel NexFET device against related products,and conducts research on key technologies to reduce the surface electric field and output capacitance of the device.The main research contents of this thesis are as follows:1.The working principle and technical characteristics of Source down NexFET structure and Drain down NexFET are compared and analyzed.At the same time,device process is designed.The key structure and process parameters of the device are analyzed,and combined with the analysis results,a 20 V P-channel NexFET device that meets the design specifications is designed,and the device layout design is completed.2.Research on the key technology of reducing the surface electric field of NexFET devices is carried out,and a P-channel NexFET device structure with a double field plate structure is proposed.The structure improves the surface electric field strength of the P LDD region through the double field plate structure,thereby reducing the peak value of the surface electric field and improving the reliability of the device.At the same time,the double field plate structure can strengthen the charge balance between the field plate and the P LDD region,so that the Miller capacitance of the device can be optimized to a certain extent,and the switching performance of the device can be improved.According to the simulation results,compared with the traditional Source down NexFET structure,the peak value of the electric field intensity at the bottom of the surface gate of the P-channel NexFET device structure with the dual field plate structure is reduced from3.25×10~5 V/cm to 2.75×10~5 V/cm and the device Miller capacitance is reduced from 24.8p F to 15.6 p F.3.Research on the key technology of reducing the output capacitance of the device is carried out,and a P-channel NexFET device structure with a Triple RESURF structure is proposed.The N-buried layer is introduced into the structure to enhance the depletion degree of the P LDD region and reduce the output capacitance and Miller capacitance of the device.According to the simulation results,the output capacitance of the device is reduced from 997 p F to 773 p F,and the Miller capacitance of the device is reduced from24.8 p F to 7.3 p F.In addition,a P-channel NexFET device with a P-buried layer is proposed.This structure introduces a P-buried layer.When the drain voltage increases to a certain level,the depletion region is connected,the width of the depletion region is widened,the output capacitance of the device is reduced,and the withstand voltage of the device is improved.According to the simulation results,the output capacitance of the device is determined by 997 p F is reduced to 917 p F,and the absolute value of device breakdown voltage increased from 28.8 V to 39.6 V.