Design And Implementation Of High-speed Acquisition System Based On Time-alternating Sampling

With the rapid development of society,high-speed data acquisition technology has been widely used in nuclear explosion detection,software radio,5G communication,medical instruments and other fields.However,high-speed analog to digital converter(ADC),as a key component of the high-speed acquisition system,is strictly controlled by western countries and is forbiddent to be exported to China.Therefore,only relatively low-speed domestic ADC can be selected to realize high-speed acquisition function.The proposed of time-alternating sampling technology breaks through the bottleneck between sampling rate and resolution of single-chip ADC,and provides a way to solve the above problems.However,the bias,gain and sampling time mismatch between each channel seriously affect the working performance of the system in the application process.Firstly,three kinds of mismatch mechanisms are studied to solve the problem of channel mismatch.The relationship between mismatch and channel number and sampling rate is deduced mathematically.The error model is established,which provides reference for hardware system design and error calibration algorithm.Then,in view of the different degrees of noise introduced by analog signals,analog devices and impedance matching in the hardware circuit,a mathematical model of the system power supply network is established,and the target impedance of the entire power supply network is obtained.Then,using the low impedance characteristic of the decoupling capacitor device at high frequency,the decoupling capacitor value at the pin end of the chip is obtained through calculation and simulation to reduce the impedance on the power supply network.At the same time,the design of the single-ended to differential circuit and the low-jitter high-speed clock circuit ensures the quality of the analog signal link.Finally,after studying the existing theoretical methods at home and abroad,the calibration scheme is divided into two aspects: estimation and calibration.Aiming at the problem that time error has the greatest influence on system performance,an adaptive time error estimation algorithm based on first-order statistics is proposed,which can estimate the error without input of reference signal.At the same time,the time error estimation strategy is proposed for the existing four-channel TIADC system structure,which can get the estimation result of the channel more quickly for the even number of channels.Secondly,the Lagrange interpolation Farrow delay filter is used to correct the time error.The traditional filter structure is improved without changing the structure and coefficients of the filter.Parallel operation is realized by time-sharing principle and hardware resource consumption is reduced.Simulation and test results show that the data acquisition function of the system is normal.The error correction algorithm can accurately estimate the time mismatch error,effectively suppress the stray components,improve the dynamic performance of the system,and verify the feasibility of the design and the effectiveness of the algorithm.