Design Of Verification Platform Based On RISC-V Processor Execution Unit

With the ever-expanding scale of integrated circuits and the integrated circuit market,the number of design codes has increased significantly,the division of labor by designers has become more refined,and the division of functional modules has become more refined.Therefore,the verification work is also more difficult and time-consuming.also grew.As the microprocessor with the most complex chip design,it puts forward higher requirements for the functional verification method.The traditional verification method is no longer suitable for the verification requirements of the current microprocessor market for development cost,development cycle and safety,and it is urgent to study more efficient and flexible verification methods.In chip research,the RISC-V instruction set has become a new direction for the development of domestic and foreign microprocessors due to its flexible,open source,streamlined,and customizable features.However,as a new reduced instruction set,the SPIKE reference model verified by the RISC-V instruction set processor has the problems that the memory access is not flexible enough and the model coverage is not comprehensive enough.This topic is aimed at the microprocessor of RISC-V instruction set,and studies the safety and reliability of its core module execution unit(Execute Unit,EXU).The execution unit is a very core part of the processor chip,responsible for the decoding and For functions such as execution,the verification space is huge,the amount of design code is lengthy,and the verification process is difficult to cover all function points,so the verification takes a lot of time and it is difficult to cover the boundary conditions.In view of the above problems,this thesis conducts research from the following aspects:(1)By studying the RISC-V instruction set processor execution unit,analyzing the RISC-V instruction set characteristics,functional characteristic documents and other processor verification experience,the function points to be tested are divided,and a reliable function model of the RISC-V processor execution unit is constructed.(2)In response to the requirements of efficient and flexible verification methods,UVM(Universal Verification Methodology)verification methodology was introduced,and a verification platform with reusable,configurable and randomly generated incentives was designed.In terms of incentive generation,the phase,sequence and factory mechanisms integrated by UVM are used to build an efficient constrained random instruction generator and random exception and interrupt incentives,which can generate a large number of random test vectors in a short time;In the interrupt and exception verification design,the assertion insertion point is designed,the correctness of the response state of the processor exception and the interrupt mechanism is monitored in real time,and the error is quickly located,realizing an efficient verification environment with reusability and random excitation.At the same time,by adding configurable and flexible components,the application of different verification scenarios can be realized.(3)Aiming at the problem that the reference model SPIKE library of RISC-V instruction set has inflexible memory access and is constrained by the address specified by the SPIKE library,a hierarchical idea is proposed.According to whether the instruction accesses the address,the memory access instruction reference model and non-memory access instructions are hierarchically designed.The reference model successfully improves the verification efficiency of memory access instructions.At the same time,a reference model of custom instructions is designed to make up for the problem of insufficient coverage of the SPIKE library.The verification platform can automatically collect coverage,and at the same time has the function of automatically printing error information,which can quickly locate the error location,analyze the cause of the error,reduce the verification time,and improve the verification efficiency.The simulation results show that the verification platform can effectively detect design problems and quickly locate them,with a functional coverage rate of about 100% and a code coverage rate of about 98% or more,with good efficiency and flexibility.