Design And Verification Of Scalar Processing Unit Based On RISC-V Instruction Set

With the development of chip technology,the Internet of Things technology is evolving in the orientation of intelligence,accelerating the pace of people's realization of intelligent life.In the terminal facilities of the Internet of Things,there is a core chip called processor.These processor chips can implement functions such as image recognition,voice recognition,gesture recognition,and smart driving.These processors have relatively higher requirements for power consumption and area.Traditional chip instruction set architectures such as x86 and ARM architectures often require high licensing fees and core technologies are easily controlled due to the protection of intellectual property rights.Reduced Instruction Set Computering is an open source instruction set architecture that has the advantages of user definability,superior performance,and strong scalability.This article will complete the design of the Scalar Processing Unit(SPU)in the Neural-network Processing Unit(NPU)based on the RISC-V instruction set with Verilog HDL,and use the Universal Verification Methodology(UVM)to verify the module.The main work is as follows:1.Analyze the advantages of the RISC-V instruction set,and based on this instruction set,complete the design of SPU in the NPU,and conduct a logical synthesis of the design.This module includes a four-stage pipeline,realizes the basic instruction set of RISC-V 32 I,and realizes the functions of jump control and configuration registers in the NPU.2.Build a corresponding verification platform for the SPU module.The verification platform has multiple driver components,scoreboard components and other components,and has the advantages of reusability and strong portability.3.On the basis of the built verification environment,develop different test cases to verify the SPU.The operation process of some RISC-V instructions is analyzed in combination with the waveform..In the later stage of the verification,the coverage of the regression test is collected to measure the progress of the verification.