Research And Implementation Of RISC-V Architecture Processor Based On PyHCL

As the core carrier of information,the processor plays an important role in people's work,study and life.With the diversification and complexity of processor usage scenarios,the design complexity of processors is increasing.Directly adopting the traditional hardware design by Verilog HDL and the UVM verification method,the low density of design code and the complexity of verification methods require high programming ability and design experience of developers.These factors restrict the rapid development of semiconductor digital design.The object-oriented agile design method is becoming the mainstream and trend of digital chip design.This paper is devoted to the study of PyHCL hardware construction language based on Python and the rapid development of RISC-V architecture five-stage pipeline processor and BIU bus with the help of its object-oriented high-level language features.A verification framework based on Python is proposed to complete the simulation and verification test of the processor.The whole design process breaks the boundary between high-level language and lowlevel hardware,realizes the unity of "Python" from the agile design of processor to the simulation verification,and finally deploys to FPGA to run correctly.The specific research contents of this paper are as follows:(1)This paper studies the RV32 I reduced instruction set in RISC-V open source instruction set architecture,introduces the function of the instruction,analyzes the instruction encoding format and instruction characteristics in detail,and summarizes the reasons for the simplicity and efficiency of the instruction.(2)This paper introduces PyHCL hardware construction language based on python,analyzes the feasibility and advantages of adopting agile design method and PyHCL programming language in hardware system design,and illustrates the specific usage and characteristics of PyHCL with cases.(3)Based on the PyHCL programming language,the RV32 I instruction set is used to design a five-stage pipeline processor of the RISC-V architecture.The BIU bus is researched and designed to improve the processor's functional realization.(4)In this paper,a verification framework based on Python is proposed,which generates large-scale test instructions with riscv-tests open-source tools,uses cocotb to write Python test files,calls Verilator emulator to complete the simulation and verification test of the processor,integrates Vivado software to synthesize and implement Verilog code,and prototype it on the Artix-7 FPGA platform of the Nexys4 development board.In this paper,the agile design methodology is used to design RISC-V processor with PyHCL programming language instead of traditional HDL programming,which effectively reduces the design threshold of the processor.The verification framework based on Python is used to complete the verification of the processor,and the innovation of the whole Python stack from the design to the verification process of the processor is realized.In addition,this design scheme provides a new idea for accelerating the design process of modern processor.