Font Size: a A A

Research On Interface Charge Compensation Mechanism And Structure Of High-K Power Mos Device

Posted on:2022-05-19Degree:MasterType:Thesis
Country:ChinaCandidate:Y F GongFull Text:PDF
GTID:2518306740951789Subject:IC Engineering
Abstract/Summary:PDF Full Text Request
Power semiconductor devices play an increasingly important role in the entire electronics industry.As one of the power semiconductor devices—power Metal Oxide Semiconductor(MOS)transistor,it has been widely used.The emergence of Super-Junction(SJ)structure has improved the trade-off between breakdown voltage(BV)and specific on-resistance(Ron,sp),but the performance of the SJ structure is susceptible to the impact of charge imbalance,and then power MOS device has been developed into High-K(HK)structure.In this structure,the existence of interface charge has a great impact on the performance of the device.Due to the deterioration of performance in this device caused by interface charge,charge compensation principles in two-dimensional(2D)and three-dimensional(3D)are proposed.According to the charge compensation,the corresponding device with compensation is designed to reduce the impact of interface charge on performance of device.The specification is given as follows:First,the mechanism of the High-K voltage sustaining layer is analogized.From compensation simulation results and mathematical models,based on the 2D High-K vertical MOS(HK-VDMOS)device,it is proved that the device can significantly improve the trade-off relationship between Ron,sp and BV.In addition,the parameters of the 3D High-K lateral SOILDMOS(HK-SOILDMOS)device are optimized,and the results show that compared with conventional SOILDMOS(Con-SOILDMOS)device,the BV is increased by12.77%,and the Ron,sp is reduced by 18.18%.Secondly,the effects of the interface charge of positive or negative on HK-VDMOS device and HK-SOILDMOS device are studied.2D and 3D charge compensation principles are also proposed to design compensation structures.After parameter optimization,it is found that the Ron,sp-BV curve of the compensated HK-VDMOS device is almost close to a linear function;the optimized BV and Ron,sp of the compensated HK-SOILDMOS device is close to the ones of(BV=212 V,Ron,sp=29.8 m??cm2)in the HK-SOILDMOS device,respectively.Finally,take utilization of the characteristic that the linear drift region can be modulated by the electric field in the HK-SOILDMOS device,three new structures with linear drift region are designed:i)variation of thickness HK-SOILDMOS(VTHK-SOILDMOS)device;ii)variable width HK-SOILDMOS(VWHK-SOILDMOS)device;and iii)variable doping HK-SOILDMOS(VDHK-SOILDMOS)device.After optimization,compared with the HK-SOILDMOS device,the BVs of the three devices are increased by 24.53%,58.49%,and73.59%,respectively.For this three devices with negative interface charge,the corresponding compensation structures are designed according to 3D charge compensation principle proposed in this paper.After parameter optimization,compared with structures without compensation,the BV of structures with compensation is enhanced to be 246.67%,60.53%,and 100%respectively.In addition,the introduction of the compensation region increases the total charge in the drift region,so the Ron,sp is also reduced.
Keywords/Search Tags:High-K dielectric, MOS device, interface charge, breakdown voltage, specific on-resistance, linear drift region
PDF Full Text Request
Related items